公开(公告)号：US20180366484A1

公开(公告)日：2018-12-20

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78648 ,  H01L29/792

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US10319732B2

公开(公告)日：2019-06-11

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US20180322912A1

公开(公告)日：2018-11-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C11/225 ,  G11C16/0466 ,  G11C16/06 ,  H01L29/78391 ,  H01L29/7841

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US10176859B2

公开(公告)日：2019-01-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C16/24 ,  G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US10033383B1

公开(公告)日：2018-07-24

申请号：US15463316

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Duenkel ,  Sven Beyer

IPC: H03K19/00 ,  H03K19/0185 ,  H01L29/78

Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

公开(公告)号：US10388514B2

公开(公告)日：2019-08-20

申请号：US15729815

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lars Mueller-Meskamp ,  Stefan Duenkel

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L21/265 ,  H01L21/223 ,  H01L29/06 ,  H01L29/66

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

公开(公告)号：US20190108998A1

公开(公告)日：2019-04-11

申请号：US15729815

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lars Mueller-Meskamp ,  Stefan Duenkel

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L21/265 ,  H01L21/223 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/02299 ,  H01L21/02172 ,  H01L21/02181 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66477 ,  H01L29/78391 ,  H01L29/7841

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.