公开(公告)号：US09735061B1

公开(公告)日：2017-08-15

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min-gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC: H01L21/44 ,  H01L21/31 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.