公开(公告)号：US08815659B2

公开(公告)日：2014-08-26

申请号：US13716686

申请日：2012-12-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Nam Sung Kim

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

Abstract translation: 形成FinFET器件的方法包括执行外延生长工艺以在半导体衬底上形成半导体材料层，其中半导体材料层的第一部分将成为FinFET器件的鳍结构，并且其中多个第二 半导体材料层的部分将成为FinFET器件的源极/漏极结构，在鳍状结构的至少一部分周围形成栅极绝缘层，并在栅极绝缘层的上方形成栅电极。

公开(公告)号：US20140167120A1

公开(公告)日：2014-06-19

申请号：US13716686

申请日：2012-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Nam Sung Kim

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

Abstract translation: 形成FinFET器件的方法包括执行外延生长工艺以在半导体衬底上形成半导体材料层，其中半导体材料层的第一部分将成为FinFET器件的鳍结构，并且其中多个第二 半导体材料层的部分将成为FinFET器件的源极/漏极结构，在鳍状结构的至少一部分周围形成栅极绝缘层，并在栅极绝缘层的上方形成栅电极。

公开(公告)号：US08846464B1

公开(公告)日：2014-09-30

申请号：US13799814

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L21/338 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US20140319624A1

公开(公告)日：2014-10-30

申请号：US14327712

申请日：2014-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Nam Sung Kim

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

公开(公告)号：US20140273389A1

公开(公告)日：2014-09-18

申请号：US13799814

申请日：2013-03-13

Applicant: Globalfoundries Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US20140231960A1

公开(公告)日：2014-08-21

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nam Sung Kim ,  Roderick M. Miller ,  Shesh M. Pandey ,  Jagar Singh

IPC: H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的开口组限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。

公开(公告)号：US08946039B2

公开(公告)日：2015-02-03

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Roderick Miller ,  Nam Sung Kim

IPC: H01L21/8222 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的一组开口限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。