公开(公告)号：US10290634B2

公开(公告)日：2019-05-14

申请号：US15001903

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/306 ,  H01L21/8234

Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.

公开(公告)号：US20190123160A1

公开(公告)日：2019-04-25

申请号：US16190549

申请日：2018-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10204991B2

公开(公告)日：2019-02-12

申请号：US15482086

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu ,  Min-hwa Chi

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/732

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US10164041B1

公开(公告)日：2018-12-25

申请号：US15790216

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10056331B2

公开(公告)日：2018-08-21

申请号：US15724563

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Suraj K. Patil ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US10038096B2

公开(公告)日：2018-07-31

申请号：US14847462

申请日：2015-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/311 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/66818

Abstract: A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping, after removal of the dummy gate and before a replacement metal gate is formed.

公开(公告)号：US10032910B2

公开(公告)日：2018-07-24

申请号：US14695411

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3115 ,  H01L29/165

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

公开(公告)号：US10003302B2

公开(公告)日：2018-06-19

申请号：US15496049

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L29/739 ,  H03C3/14 ,  H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H03D7/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

公开(公告)号：US20180151238A1

公开(公告)日：2018-05-31

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US09964605B2

公开(公告)日：2018-05-08

申请号：US15190323

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  G01R33/06 ,  H01L29/06 ,  H01L29/78 ,  H01L29/82

CPC classification number: G01R33/066 ,  G01R33/0058 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/82

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.