公开(公告)号：US20200075738A1

公开(公告)日：2020-03-05

申请号：US16121014

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3213

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.

公开(公告)号：US20180122891A1

公开(公告)日：2018-05-03

申请号：US15848324

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09923046B1

公开(公告)日：2018-03-20

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US10374029B2

公开(公告)日：2019-08-06

申请号：US15848324

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/06

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US20140231960A1

公开(公告)日：2014-08-21

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nam Sung Kim ,  Roderick M. Miller ,  Shesh M. Pandey ,  Jagar Singh

IPC: H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的开口组限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。

公开(公告)号：US10741656B2

公开(公告)日：2020-08-11

申请号：US16121014

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3213

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.

公开(公告)号：US10236213B1

公开(公告)日：2019-03-19

申请号：US15917940

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh M. Pandey ,  Jiehui Shu ,  Hui Zang ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate conductor of a first finFET from an end of a second metal gate conductor of a second finFET. The gate cut structure includes a body contacting the end of the first and second metal gate conductors. A liner spacer separates a lower portion of the body from an interlayer dielectric (ILD), and an upper portion of the body contacts the ILD. During formation, the liner spacer allows for a larger gate cut opening to be used to allow quality cleaning of the gate cut opening, but also reduction in size of the spacing between metal gate conductor ends of the finFETs. In one example, the body may have a lower portion having a width less than an upper portion thereof.

公开(公告)号：US20200227404A1

公开(公告)日：2020-07-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/522

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

公开(公告)号：US20180083089A1

公开(公告)日：2018-03-22

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.