公开(公告)号：US20150108580A1

公开(公告)日：2015-04-23

申请号：US14580834

申请日：2014-12-23

Applicant: Globalfoundries Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/735 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。

公开(公告)号：US20150001634A1

公开(公告)日：2015-01-01

申请号：US13930611

申请日：2013-06-28

Applicant: Globalfoundries Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

公开(公告)号：US09159667B2

公开(公告)日：2015-10-13

申请号：US13951654

申请日：2013-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L21/8238 ,  H01L23/525 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

公开(公告)号：US09087706B2

公开(公告)日：2015-07-21

申请号：US14580834

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/735

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

公开(公告)号：US20150340319A1

公开(公告)日：2015-11-26

申请号：US14817546

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

公开(公告)号：US08975130B2

公开(公告)日：2015-03-10

申请号：US13930611

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。

公开(公告)号：US08946039B2

公开(公告)日：2015-02-03

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Roderick Miller ,  Nam Sung Kim

IPC: H01L21/8222 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的一组开口限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。