公开(公告)号：US09026977B2

公开(公告)日：2015-05-05

申请号：US13968850

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc Tarabbia ,  Norman Chen ,  Jian Liu ,  Nader Magdy Hindawy ,  Tuhin Guha Neogi ,  Mahbub Rashed ,  Anurag Mittal

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/06 ,  G06F2217/78

Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Abstract translation: 一种方法包括将标准单元库的多个单元电连接到电源轨。 沉积接触区以连接多个单元的单元的第一有源区和第二有源区。 第一区域和第二区域位于轨道的相对侧并且电连接到不同的排水沟。 接触区域使用通孔电连接到电源轨。 接触区域被屏蔽以去除接触区域的一部分以将第一活性物质与第二活性区域电分离。

公开(公告)号：US10833018B2

公开(公告)日：2020-11-10

申请号：US16502521

申请日：2019-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US09087706B2

公开(公告)日：2015-07-21

申请号：US14580834

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/735

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

公开(公告)号：US20140173533A1

公开(公告)日：2014-06-19

申请号：US13717816

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuyang Sun ,  Chidambaram Kallingal ,  Marc Tarabbia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract translation: 提供了清洁/分辨光刻热点的方法（例如，在半导体设计的模拟阶段期间）。 通常，将在光刻图案或轮廓的第一多边形（具有第一颜色）中识别热点。 一旦确定了热点，将识别靠近热点的位置（例如，具有第一颜色的第一多边形的另一部分或具有第一颜色的第二多边形），以放置针迹标记。 一旦识别出位置，将在该位置放置一个针迹标记。 然后，将针迹标记位置的颜色改变为第二颜色，并且可以进一步处理所得到的平版印刷图案以清洁/解析热点。

公开(公告)号：US20150108580A1

公开(公告)日：2015-04-23

申请号：US14580834

申请日：2014-12-23

Applicant: Globalfoundries Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/735 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。

公开(公告)号：US20130328205A1

公开(公告)日：2013-12-12

申请号：US13490840

申请日：2012-06-07

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation ,  STMircoelectronics Inc.

Inventor： Frank Johnson ,  Olivier Menut ,  Marc Tarabbia ,  Gregory A. Northrop

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11859 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括具有第一边界，与第一边界相反的第二边界，互连第一和第二边界的第三边界以及与第三边界相对的第四边界并互连第一和第二边界的标准单元。 标准单元还包括从第一边界延伸到第二边界的并行有效区域。 此外，标准单元具有从第三边界延伸到第四边界并且在有源区上延伸的平行栅极条。 切割掩模覆盖门条。 互连件定位在切割掩模上方并与选定的栅条形成电连接。

公开(公告)号：US20210013150A1

公开(公告)日：2021-01-14

申请号：US17039187

申请日：2020-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

公开(公告)号：US08987816B2

公开(公告)日：2015-03-24

申请号：US14519902

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Stephens ,  Marc Tarabbia ,  Nader Hindawy ,  Roderick Augur

IPC: H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L29/49 ,  G06F17/50

CPC classification number: H01L23/481 ,  G06F17/5077 ,  H01L21/76877 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/41725 ,  H01L29/4916 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2924/0002 ,  Y02T10/82 ,  H01L2924/00

Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.

Abstract translation: 提供了使用三掩模分解处理形成CA电力轨道的方法和所得到的装置。 实施例包括使用第一颜色掩模在半导体衬底的有源层中形成水平扩散CA电力轨道; 使用第二和第三颜色掩模在有源层中形成多个垂直CA，垂直CA将CA电力轨连接到半导体衬底上与CA电力轨道间隔开的至少一个扩散区，其中每对CA由 第二和第三彩色掩模中的一个被至少两个间距分开。

公开(公告)号：US20150001634A1

公开(公告)日：2015-01-01

申请号：US13930611

申请日：2013-06-28

Applicant: Globalfoundries Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

公开(公告)号：US08869075B2

公开(公告)日：2014-10-21

申请号：US13717816

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidambaram Kallingal ,  Marc Tarabbia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract translation: 提供了清洁/分辨光刻热点的方法（例如，在半导体设计的模拟阶段期间）。 通常，将在光刻图案或轮廓的第一多边形（具有第一颜色）中识别热点。 一旦确定了热点，将识别靠近热点的位置（例如，具有第一颜色的第一多边形的另一部分或具有第一颜色的第二多边形），以放置针迹标记。 一旦识别出位置，将在该位置放置一个针迹标记。 然后，将针迹标记位置的颜色改变为第二颜色，并且可以进一步处理所得到的平版印刷图案以清洁/解析热点。