公开(公告)号：US09123773B1

公开(公告)日：2015-09-01

申请号：US14461015

申请日：2014-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： HongLiang Shen ,  Fangyu Wu ,  Haigou Huang ,  Xusheng Wu ,  Changyong Xiao ,  Wanxum He

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/76232 ,  H01L29/66795

Abstract: Methods of forming a T-shaped SBD using a single-mask process flow are disclosed. Embodiments include providing a substrate having STI regions; forming a hard mask layer over the substrate and the STI regions, the hard mask having an opening laterally separated from the STI regions; forming a recess in the substrate through the opening, the recess having a first width; forming spacers on sidewalls of the recess, with a gap therebetween; forming a trench in the substrate through the gap, the trench having a second width less than the first; removing the spacers; removing the hard mask layer; filling the trench and the recess with an oxide layer, forming a T-shaped STI region; forming another hard mask layer on a portion of the T-shaped STI region; and revealing a Fin by removing portions of the STI regions and the T-shaped STI region.

Abstract translation: 公开了使用单掩模工艺流程形成T形SBD的方法。 实施例包括提供具有STI区域的基板; 在所述基板和所述STI区域上形成硬掩模层，所述硬掩模具有与所述STI区域横向分离的开口; 通过所述开口在所述基板中形成凹部，所述凹部具有第一宽度; 在凹槽的侧壁上形成间隔物，其间具有间隙; 通过所述间隙在所述衬底中形成沟槽，所述沟槽具有小于所述第一宽度的第二宽度; 去除垫片; 去除硬掩模层; 用氧化物层填充沟槽和凹部，形成T形STI区域; 在T形STI区域的一部分上形成另一个硬掩模层; 并且通过去除STI区域和T形STI区域的部分来显露Fin。

公开(公告)号：US20160190130A1

公开(公告)日：2016-06-30

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹陷之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US20150340319A1

公开(公告)日：2015-11-26

申请号：US14817546

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

公开(公告)号：US09455198B1

公开(公告)日：2016-09-27

申请号：US14676034

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Lun Zhao ,  Richard J. Carter ,  Xusheng Wu

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Abstract translation: 本文公开的一种说明性方法包括除去第一图案化掩模层中的多个第一特征中的至少一个但不是全部的，以便限定经修改的第一图案化掩模层，其中去除的第一特征 对应于将形成最终隔离结构的位置，通过经修改的第一图案化掩模层执行蚀刻工艺，以在衬底中形成初始隔离沟槽，以及通过修改的第一图案化掩模层执行另一蚀刻工艺，由此限定 在衬底中的多个翅片形成沟槽并且延伸初始隔离沟槽的深度，以便限定用于最终隔离结构的最终隔离沟槽。

公开(公告)号：US09362176B2

公开(公告)日：2016-06-07

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhao Lun ,  Zhenyu Hu ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US09159667B2

公开(公告)日：2015-10-13

申请号：US13951654

申请日：2013-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L21/8238 ,  H01L23/525 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

公开(公告)号：US09406676B2

公开(公告)日：2016-08-02

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹槽之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US09368496B1

公开(公告)日：2016-06-14

申请号：US14609614

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen

IPC: H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L21/70 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Methods for creating uniform source/drain cavities filled with uniform levels of materials in an IC device and resulting devices are disclosed. Embodiments include forming a hard mask on an upper surface of a Si substrate, the hard mask having an opening over a STI region formed in the Si substrate and extending over adjacent portions of the Si substrate; forming low-k dielectric spacers on a lower portion of sidewalls of the opening, the spacers being formed between the sidewalls and the STI region; filling the opening with an oxide; removing the hard mask; removing an upper portion of the oxide and a portion of the low-k dielectric spacers; revealing a Si fin in the Si substrate; forming equally spaced gate electrodes, each having sidewall spacers, over the Si fin and the oxide; and forming source/drain regions in the Si fin between each pair of adjacent gate electrodes.

Abstract translation: 公开了在IC器件和所产生的器件中产生均匀的源/漏腔的填充均匀水平的材料的方法。 实施例包括在Si衬底的上表面上形成硬掩模，所述硬掩模在形成于所述Si衬底中并在所述Si衬底的相邻部分上延伸的STI区域上具有开口; 在所述开口的侧壁的下部形成低k电介质间隔物，所述间隔物形成在所述侧壁和所述STI区域之间; 用氧化物填充开口; 去除硬面膜; 去除氧化物的上部和低k电介质间隔物的一部分; 在Si衬底中露出Si鳍; 在所述Si翅片和所述氧化物上形成均匀间隔开的栅电极，每个栅电极具有侧壁间隔物; 以及在每对相邻栅电极之间的Si鳍中形成源/漏区。

公开(公告)号：US09087870B2

公开(公告)日：2015-07-21

申请号：US13904626

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Huang Liu ,  HongLiang Shen ,  Jin Ping Liu ,  Seung Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括蚀刻设置在两个相邻散热片之间的STI沟槽中的增强的高纵横比工艺（eHARP）氧化物填充物，以形成凹陷的eHARP氧化物填充物。 两个相邻的翅片从体半导体衬底延伸。 覆盖凹陷的eHARP氧化物填充物形成硅层。 将硅层转化为热氧化物层，以进一步用氧化物材料填充STI沟槽。

公开(公告)号：US08969205B2

公开(公告)日：2015-03-03

申请号：US13852496

申请日：2013-03-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： HongLiang Shen ,  Dae-Han Choi ,  Dae Geun Yang ,  Jung Yu Hsieh

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/3086 ,  H01L21/28114 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.

Abstract translation: 制造中的中间半导体结构包括硅半导体衬底，在衬底上的氮化硅（SiN）的硬掩模和在硬掩模上的多晶硅或非晶硅的牺牲层。 牺牲层被图案化成侧壁间隔物，用于与侧壁间隔物例如可流动氧化物的组成基本上不同的填充材料的心轴。 去除心轴使得侧壁间隔件具有提供粗糙三角形形状的垂直锥形内侧壁和外侧壁。 粗糙的三角形侧壁间隔物用作硬掩模以在下面对SiN硬掩模进行图案化。