公开(公告)号：US20160071932A1

公开(公告)日：2016-03-10

申请号：US14480974

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

公开(公告)号：US20160322260A1

公开(公告)日：2016-11-03

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Sukwon HONG ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

Abstract translation: 本申请涉及光学平坦化层蚀刻工艺。 实施例包括形成由电介质层分离的翅片; 在每个翅片的每一侧上的电介质层中形成凹槽，每个凹槽用于金属栅极; 在每个凹部的每一侧上形成侧壁间隔物; 在每个凹部和每个翅片的顶表面上沉积高k电介质衬垫; 在高k电介质层上沉积金属衬垫; 在所述电介质层的顶表面上沉积非共形有机层（NCOL）以夹紧每个凹部的顶部; 在NCOL上放置OPL和ARC; 在第一区域中的电介质层的一部分和凹部上蚀刻OPL，ARC和NCOL; 并且蚀刻所述凹部的所述部分以除去存在于所述凹部的所述部分的每个凹部的底部的残留NCOL。

公开(公告)号：US20160204265A1

公开(公告)日：2016-07-14

申请号：US15077153

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract translation: 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。