Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.
Abstract:
A method and apparatus for hybrid test pattern generation for optical proximity correction (OPC) model calibration is disclosed. Embodiments may include receiving a mask pattern of a chip layout, extracting one or more patterns from the mask pattern, determining one or more parametric data sets for the one or more patterns, retrieving one or more calibration parametric data sets based on one or more other mask patterns, determining a difference between the one or more parametric data sets and the one or more calibration parametric data sets, and adding the one or more parametric data sets to the one or more calibration parametric data sets if the difference satisfies a threshold value.