公开(公告)号：US20190229207A1

公开(公告)日：2019-07-25

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/761

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US10361293B1

公开(公告)日：2019-07-23

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L21/761 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/02

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US10096587B1

公开(公告)日：2018-10-09

申请号：US15794688

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mickey Yu ,  Alain Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  You Li ,  Robert J. Gauthier, Jr.

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06

Abstract: Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.

公开(公告)号：US10692852B2

公开(公告)日：2020-06-23

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, Jr.

IPC: H01L29/74 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US20200135715A1

公开(公告)日：2020-04-30

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, JR.

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US10541236B2

公开(公告)日：2020-01-21

申请号：US16018549

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Souvick Mitra ,  Mickey Yu ,  Alain F. Loiseau ,  You Li ,  Robert J. Gauthier, Jr. ,  Tsung-Che Tsai

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.

公开(公告)号：US10290626B1

公开(公告)日：2019-05-14

申请号：US15870238

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： You Li ,  Alain Loiseau ,  Tsung-Che Tsai ,  Mickey Yu ,  Souvick Mitra ,  Robert Gauthier, Jr.

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/285 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L23/535

Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.