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    VERTICAL CONSTRUCTIONS FOR DEVICES HAVING A DRIFT REGION
    1.
    发明申请
    VERTICAL CONSTRUCTIONS FOR DEVICES HAVING A DRIFT REGION 审中-公开

    公开(公告)号：US20200098909A1

    公开(公告)日：2020-03-26

    申请号：US16137739

    申请日：2018-09-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Robert Gauthier, JR. ,  Souvick Mitra ,  Alain Loiseau ,  Tsai Tsung-Che ,  Mickey Yu ,  You Li

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

    Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

    Vertical fin-type devices and methods
    2.
    发明授权
    Vertical fin-type devices and methods 有权

    公开(公告)号：US10361293B1

    公开(公告)日：2019-07-23

    申请号：US15878478

    申请日：2018-01-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

    IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L21/761 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/02

    Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

    ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE
    4.
    发明申请
    ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE 有权
    静电放电和被动结构集成在栅栏栅极型场效应二极管

    公开(公告)号：US20160379972A1

    公开(公告)日：2016-12-29

    申请号：US15140516

    申请日：2016-04-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

    Abstract translation: 场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。 阳极位于翅片的顶面，阴极位于平面部分的端面。 翅片和平面部分的垂直度导致阳极和阴极彼此垂直。 第一栅极绝缘体在顶表面和平面部分之间接触翅片。 第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体和鳍的表面之间。 另外，第二栅极绝缘体接触端面和鳍之间的平面部分。 第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

    VERTICAL FIN-TYPE DEVICES AND METHODS
    7.
    发明申请
    VERTICAL FIN-TYPE DEVICES AND METHODS 审中-公开

    公开(公告)号：US20190229207A1

    公开(公告)日：2019-07-25

    申请号：US15878478

    申请日：2018-01-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

    IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/761

    Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

    Self-healing electrostatic discharge power clamp
    10.
    发明授权
    Self-healing electrostatic discharge power clamp 有权
    自愈式静电放电电源钳

    公开(公告)号：US09425185B2

    公开(公告)日：2016-08-23

    申请号：US14290141

    申请日：2014-05-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  You Li ,  Souvick Mitra

    IPC: H02H9/00 ,  H01L27/02 ,  H01L23/525 ,  H01G17/00 ,  H01G13/00

    CPC classification number: H01L27/0266 ,  H01G13/00 ,  H01G17/00 ,  H01L23/5256 ,  H01L27/0285 ,  H01L2924/0002 ,  Y10T29/435 ,  H01L2924/00

    Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

    Abstract translation: 制造提供静电放电保护的电路的电路和方法，以及保护集成电路免受静电放电的方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，以及与节点处的定时电路耦合的功率钳位装置。 电容器包括多个电容器元件。 保护电路还包括多个电子保险丝。 每个电子熔断器与相应的一个电容器元件耦合。 场效应晶体管可以与定时电路的电阻并联耦合，并且可以用于旁路电阻器以向与异常低阻抗的电容器元件耦合的任何电子熔丝提供编程电流。

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