公开(公告)号：US20190229207A1

公开(公告)日：2019-07-25

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/761

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US20170229443A1

公开(公告)日：2017-08-10

申请号：US15497924

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

公开(公告)号：US20200135715A1

公开(公告)日：2020-04-30

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, JR.

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US20160379972A1

公开(公告)日：2016-12-29

申请号：US15140516

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Abstract translation: 场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。 阳极位于翅片的顶面，阴极位于平面部分的端面。 翅片和平面部分的垂直度导致阳极和阴极彼此垂直。 第一栅极绝缘体在顶表面和平面部分之间接触翅片。 第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体和鳍的表面之间。 另外，第二栅极绝缘体接触端面和鳍之间的平面部分。 第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

公开(公告)号：US20160197080A1

公开(公告)日：2016-07-07

申请号：US15067307

申请日：2016-03-11

Applicant: GlobalFoundries Inc.

Inventor： John B. Campi, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0928 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835

Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.