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    Ethernet physical layer device having integrated physical coding and forward error correction sub-layers
    1.
    发明授权
    Ethernet physical layer device having integrated physical coding and forward error correction sub-layers 有权

    公开(公告)号：US10411832B2

    公开(公告)日：2019-09-10

    申请号：US15336974

    申请日：2016-10-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

    IPC: H04L1/00

    Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

    Air gap electrostatic discharge structure for high speed circuits
    2.
    发明授权
    Air gap electrostatic discharge structure for high speed circuits 有权
    用于高速电路的气隙静电放电结构

    公开(公告)号：US09380688B1

    公开(公告)日：2016-06-28

    申请号：US14985542

    申请日：2015-12-31

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Kai D. Feng ,  Yang Liu ,  Dongbing Shao ,  Zheng Xu

    IPC: H02H9/06 ,  H05F3/04 ,  H02H7/20

    CPC classification number: H05F3/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0288

    Abstract: Aspects relate to an electrostatic discharge (ESD) system for ESD protection and a method of manufacturing. The ESD system includes a lower substrate, an underfill layer that is disposed on the lower substrate that includes a plurality of cavities, and an upper substrate disposed on the underfill layer. The upper substrate includes a plurality of air ventilation shafts. The ESD system also includes a plurality of air gap metal tip structures disposed within one or more of the plurality of cavities in the underfill, wherein the plurality of ventilation shafts line up with the plurality of air gap metal tip structures. At least one air gap tip structure includes an upper metallic tip and a lower metallic tip that are placed along a vertical axis that is perpendicular to the substrates. An air cavity is provided between the upper metallic tip and the lower metallic tip forming an air chamber.

    Abstract translation: 方面涉及用于ESD保护的静电放电（ESD）系统和制造方法。 ESD系统包括下基板，设置在包括多个空腔的下基板上的底部填充层，以及设置在底部填充层上的上基板。 上基板包括多个通风轴。 ESD系统还包括设置在底部填充物中的多个空腔内的一个或多个空腔内的多个气隙金属尖端结构，其中多个通气轴与多个气隙金属尖端结构对齐。 至少一个气隙尖端结构包括沿着垂直于基底的垂直轴放置的上金属末端和下金属末端。 在上金属端头和下金属端头之间设有空气腔，形成一个空气室。

    CMOS INVERTER STRUCTURE AND METHODS OF MAKING SUCH INVERTERS
    3.
    发明申请
    CMOS INVERTER STRUCTURE AND METHODS OF MAKING SUCH INVERTERS 审中-公开

    公开(公告)号：US20190288690A1

    公开(公告)日：2019-09-19

    申请号：US15922516

    申请日：2018-03-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kong Boon Yeap ,  Yang Liu ,  Tian Shen ,  Anjum Mehta

    IPC: H03K19/0948 ,  H03K3/356 ,  H03K19/00 ,  H03K19/0185 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/786

    Abstract: One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.

    ETHERNET PHYSICAL LAYER DEVICE HAVING AN INTEGRATED PHYSICAL CODING AND FORWARD ERROR CORRECTION SUB-LAYERS
    6.
    发明申请
    ETHERNET PHYSICAL LAYER DEVICE HAVING AN INTEGRATED PHYSICAL CODING AND FORWARD ERROR CORRECTION SUB-LAYERS 审中-公开

    公开(公告)号：US20180123733A1

    公开(公告)日：2018-05-03

    申请号：US15336974

    申请日：2016-10-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

    IPC: H04L1/00

    CPC classification number: H04L1/0052 ,  H04L1/0043

    Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

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