中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.022 seconds)

    GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
    2.
    发明申请
    GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL 有权
    在大容量FINFET通道中产生拉伸应变

    公开(公告)号：US20160372598A1

    公开(公告)日：2016-12-22

    申请号：US14745547

    申请日：2015-06-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yun-Yu Wang ,  Shogo Mochizuki

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

    Abstract: Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.

    Abstract translation: 本发明的实施例提供一种形成鳍式晶体管的方法。 该方法包括在栅极结构的两个相对侧处形成具有在栅极结构下方的鳍状沟道区域的鳍状FET结构以及与鳍状沟道区域直接相邻的源极区域和漏极区域; 并且使源极区域和漏极区域受到压缩应变; 从而使源极区域和漏极区域向鳍状沟道区域施加拉伸应变。 还提供了由此形成的finFET晶体管，其包括在其顶部由栅极覆盖的鳍状通道区域; 位于栅极的第一侧上的沟道区域的第一端附近的源极; 以及在所述栅极的第二侧上的所述沟道区的第二端旁边的漏极，其中所述源极和漏极由外延生长的具有至少50％原子百分比的Ge浓度水平的硅 - 锗（SiGe）制成， 硅帽。

    3D transistor channel mobility enhancement
    3.
    发明授权
    3D transistor channel mobility enhancement 有权
    3D晶体管通道移动性增强

    公开(公告)号：US09023697B2

    公开(公告)日：2015-05-05

    申请号：US13962322

    申请日：2013-08-08

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Kevin K. Chan ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Min Yang ,  Qi Zhang

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.

    Abstract translation: 形成半导体结构的方法包括在多个鳍片的暴露部分上生长外延掺杂层。 外延掺杂层将散热片的暴露部分组合以形成合并的源极和漏极区域。 通过外延掺杂层在鳍片中发生注入工艺，以改变鳍片的晶格以形成非晶化鳍片。 氮化物层沉积在半导体结构上。 氮化物层覆盖合并的源区和漏区。 在半导体结构中进行热处理以使非晶化翅片再结晶以形成再结晶的翅片。 再结晶的翅片，外延掺杂层和氮化物层形成应变源极和漏极区域，其对沟道区域引起应力。

    Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography
    4.
    发明授权
    Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography 有权
    通过暗场电子全息术产生高空间分辨率的非变形暗场应变图的方法

    公开(公告)号：US09551674B1

    公开(公告)日：2017-01-24

    申请号：US14928605

    申请日：2015-10-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yun-Yu Wang ,  John Bruley

    IPC: G01N23/00 ,  G01N23/04

    CPC classification number: G01N23/04 ,  G01N2223/03 ,  G01N2223/607

    Abstract: An inline dark field holographic method for measuring strain in a semiconductor or other crystalline material using a transmission electron microscope having an electron gun for passing an electron beam through strained and unstrained specimens. A condenser mini-lens between the magnetic tilting coil and the specimens increases defection of the beam at an angle with prior to passing through the pair of specimens. The first objective lens forms a virtual image of each of the specimens and the second objective lens focuses the virtual images of each of the specimens at an intermediate image plane to form intermediate images of each of the specimens. The biprism creates the interference pattern between the specimens is formed at the image plane, which may then be viewed to determine the degree of strain of the strained specimen and provides a coma-free strain map with minimal optical distortion.

    Abstract translation: 一种用于使用具有电子枪的透射电子显微镜测量半导体或其它结晶材料中的应变的在线暗场全息方法，该电子枪使电子束通过应变和未受限制的样品。 在磁性倾斜线圈和试样之间的聚光镜微透镜会增加与穿过一对试样之间的角度的偏转。 第一物镜形成每个样本的虚像，第二物镜将每个样本的虚拟图像聚焦在中间像平面处以形成每个样本的中间图像。 双棱镜产生在图像平面上形成的样品之间的干涉图案，然后可以观察它们以确定应变样品的应变程度，并提供具有最小光学失真的无消耗应变图。

    Mitigation of hot carrier damage in field-effect transistors
    5.
    发明授权
    Mitigation of hot carrier damage in field-effect transistors 有权

    公开(公告)号：US10566446B2

    公开(公告)日：2020-02-18

    申请号：US15992969

    申请日：2018-05-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yun-Yu Wang ,  Jochonia Nxumalo ,  Ahmad Katnani ,  Dimitrios Ioannou ,  Kenneth Bandy ,  Jeffrey Brown ,  Michael J. MacDonald

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L23/29 ,  H01L29/40 ,  H01L21/223

    Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

    Generating tensile strain in bulk finFET channel
    6.
    发明授权
    Generating tensile strain in bulk finFET channel 有权

    公开(公告)号：US09685553B2

    公开(公告)日：2017-06-20

    申请号：US14745547

    申请日：2015-06-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yun-Yu Wang ,  Shogo Mochizuki

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

    Abstract: Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.

    MITIGATION OF HOT CARRIER DAMAGE IN FIELD-EFFECT TRANSISTORS
    9.
    发明申请
    MITIGATION OF HOT CARRIER DAMAGE IN FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20190371918A1

    公开(公告)日：2019-12-05

    申请号：US15992969

    申请日：2018-05-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yun-Yu Wang ,  Jochonia Nxumalo ,  Ahmad Katnani ,  Dimitrios Ioannou ,  Kenneth Bandy ,  Jeffrey Brown ,  Michael J. MacDonald

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/223 ,  H01L29/78 ,  H01L23/29 ,  H01L29/40

    Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Patent Agency Ranking