公开(公告)号：US10191107B2

公开(公告)日：2019-01-29

申请号：US15440791

申请日：2017-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhigang Song ,  Qian Xu ,  William Davies, Jr.

IPC: G06F7/556 ,  G01R31/28 ,  G06F17/16

Abstract: Failure types that caused defective items to fail testing are identified, the defective items are grouped by the failure types to produce failure-type groups, and the defective items are analyzed to identify defect types that caused the failures. Failure-type limited yield within each of the failure-type groups, and failure-type group-specific defect ratio based on proportions of the defect types within each of the failure-type groups are determined. Additionally, each failure-type group-specific defect ratio is weighted using the failure-type limited yield to produce a weighted failure-type group-specific defect limited yield. For each of the defect types, the weighted failure-type group-specific defect limited yield from each of the failure-type groups is combined to produce the failure-type influenced defect-type total limited yield. Matrix processing is used for the weighting and combination processes. The defect types are ranked based on the failure-type influenced defect-type total limited yield.

公开(公告)号：US09559051B1

公开(公告)日：2017-01-31

申请号：US14976417

申请日：2015-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongchun Xin ,  Jang H. Sim ,  Junjing Bao ,  Zhigang Song ,  Yunsheng Song

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/76804 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2221/1063

Abstract: A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.

Abstract translation: 用于在通孔开口电子结构中沉积导体的方法去除了通孔底部衬垫，使得沉积在通孔开口中的导体直接接触下面的导电层。 该方法包括在通孔开口侧壁和底部上的绝缘层和衬垫层上沉积非晶硅。 非晶硅基本上在整个通孔开口上延伸，同时在通孔开口内留下空隙。 在通孔开口和通孔开口底部和通孔开口底部上的衬垫层上的非晶硅被各向异性地蚀刻，以在电介质层和通孔开口侧壁上留下一层非晶硅。 然后去除非晶硅以形成具有基本上开口底部衬垫的通孔。 然后将导体沉积在通孔开口中并接触下面的导电层。

公开(公告)号：US20180238958A1

公开(公告)日：2018-08-23

申请号：US15440791

申请日：2017-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhigang Song ,  Qian Xu ,  William Davies, JR.

IPC: G01R31/28 ,  G06F17/16 ,  G06F7/556

CPC classification number: G01R31/2851 ,  G06F7/556 ,  G06F17/16

Abstract: Failure types that caused defective items to fail testing are identified, the defective items are grouped by the failure types to produce failure-type groups, and the defective items are analyzed to identify defect types that caused the failures. Failure-type limited yield within each of the failure-type groups, and failure-type group-specific defect ratio based on proportions of the defect types within each of the failure-type groups are determined. Additionally, each failure-type group-specific defect ratio is weighted using the failure-type limited yield to produce a weighted failure-type group-specific defect limited yield. For each of the defect types, the weighted failure-type group-specific defect limited yield from each of the failure-type groups is combined to produce the failure-type influenced defect-type total limited yield. Matrix processing is used for the weighting and combination processes. The defect types are ranked based on the failure-type influenced defect-type total limited yield.

公开(公告)号：US20170154687A1

公开(公告)日：2017-06-01

申请号：US14954151

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhigang Song ,  Oliver D. Patterson ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC: G11C29/04 ,  H01L21/768 ,  H01L23/58 ,  H01L21/66 ,  H01L27/11 ,  H01L27/108

CPC classification number: G11C29/04 ,  G11C29/025 ,  G11C29/56008 ,  G11C2029/0403 ,  G11C2029/5602 ,  H01L22/12 ,  H01L22/14 ,  H01L22/30 ,  H01L23/585 ,  H01L27/1104

Abstract: A SRAM-like electron beam inspection (EBI) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an IC are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact nodes of the contact layers. Voltage contrast is observed during EBI to detect short-circuits, open-circuits, or leakage currents formed between the horizontal components of the conductive mesh and metallized islands placed therebetween.