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    Active x-ray attack prevention device
    1.
    发明授权
    Active x-ray attack prevention device 有权

    公开(公告)号：US11121097B1

    公开(公告)日：2021-09-14

    申请号：US16881736

    申请日：2020-05-22

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Vibhor Jain ,  Sebastian T. Ventrone ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Ajay Raman

    IPC: H01L23/00 ,  H01L23/48

    Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.

    System and method to drive logic circuit with non-deterministic clock edge variation
    2.
    发明授权
    System and method to drive logic circuit with non-deterministic clock edge variation 有权

    公开(公告)号：US11054854B1

    公开(公告)日：2021-07-06

    申请号：US17032027

    申请日：2020-09-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Sebastian T. Ventrone ,  Johnatan Kantarovsky

    IPC: G06F1/08 ,  G06F21/75 ,  H03K3/84 ,  H03K3/037 ,  H03K5/01 ,  H03K5/00

    Abstract: Embodiments of the disclosure provide systems and methods to operate a logic circuit with non-deterministic clock edge variations. A system may include a clock coupled to a logic circuit, the logic circuit having a set of source latches coupled to a set of capture latches through a set of logic cones. The clock includes a fixed clock component configured to generate a clock signal having a first clock edge, and a jitter clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on a non-deterministic value. The clock transmits the clock signal with the second clock edge to drive the set of source latches and the set of capture latches of the logic circuit. A clock controller coupled to the jitter clock component generates the non-deterministic value.

    Anti-tamper x-ray blocking package
    6.
    发明授权
    Anti-tamper x-ray blocking package 有权

    公开(公告)号：US11437329B2

    公开(公告)日：2022-09-06

    申请号：US17070377

    申请日：2020-10-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

    Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

    Enabling of functional logic in IC using thermal sequence enabling test
    8.
    发明授权
    Enabling of functional logic in IC using thermal sequence enabling test 有权

    公开(公告)号：US11366154B2

    公开(公告)日：2022-06-21

    申请号：US16527146

    申请日：2019-07-31

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Sebastian T. Ventrone ,  Richard S. Graf ,  Ezra D. B. Hall ,  Jack R. Smith

    IPC: G01R31/02 ,  G01R31/28 ,  H04L9/32

    Abstract: An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

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