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    Semiconductor structure with in-device high resistivity polycrystalline semiconductor element and method
    2.
    发明授权
    Semiconductor structure with in-device high resistivity polycrystalline semiconductor element and method 有权

    公开(公告)号：US11545577B2

    公开(公告)日：2023-01-03

    申请号：US17114554

    申请日：2020-12-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

    IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/04

    Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

    Anti-tamper x-ray blocking package
    9.
    发明授权
    Anti-tamper x-ray blocking package 有权

    公开(公告)号：US11437329B2

    公开(公告)日：2022-09-06

    申请号：US17070377

    申请日：2020-10-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

    Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

    STRUCTURE INCLUDING RESISTOR NETWORK FOR BACK BIASING FET STACK
    10.
    发明公开
    STRUCTURE INCLUDING RESISTOR NETWORK FOR BACK BIASING FET STACK 审中-公开

    公开(公告)号：US20230188131A1

    公开(公告)日：2023-06-15

    申请号：US17643567

    申请日：2021-12-09

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

    IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/12 ,  H03K17/693

    CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

    Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

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