公开(公告)号：US12040252B2

公开(公告)日：2024-07-16

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L21/762 ,  H01L23/367 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L21/76229 ,  H01L23/367 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US12131904B2

公开(公告)日：2024-10-29

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

CPC classification number: H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US20230125584A1

公开(公告)日：2023-04-27

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US11515158B2

公开(公告)日：2022-11-29

申请号：US16815070

申请日：2020-03-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US20210296122A1

公开(公告)日：2021-09-23

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US20240014101A1

公开(公告)日：2024-01-11

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L23/367 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L21/76229 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US11195715B2

公开(公告)日：2021-12-07

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/324

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US20210287902A1

公开(公告)日：2021-09-16

申请号：US16815070

申请日：2020-03-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.