公开(公告)号：US12087764B2

公开(公告)日：2024-09-10

申请号：US17890446

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US11569374B2

公开(公告)日：2023-01-31

申请号：US17109538

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L27/088 ,  H01L29/66

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US12243923B2

公开(公告)日：2025-03-04

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US11362201B1

公开(公告)日：2022-06-14

申请号：US17120916

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sarah McTaggart ,  Qizhi Liu ,  Vibhor Jain ,  Mark Levy ,  Paula Fisher ,  James R. Elliott

IPC: H01L29/737 ,  H01L29/66

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

公开(公告)号：US20220173233A1

公开(公告)日：2022-06-02

申请号：US17109538

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/04 ,  H01L27/088 ,  H01L29/16

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US20220122963A1

公开(公告)日：2022-04-21

申请号：US17072649

申请日：2020-10-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US11264457B1

公开(公告)日：2022-03-01

申请号：US16953897

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Steven M. Shank ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/763 ,  H01L27/06 ,  H01L21/762

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

公开(公告)号：US20210296122A1

公开(公告)日：2021-09-23

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US11567277B1

公开(公告)日：2023-01-31

申请号：US17472846

申请日：2021-09-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Mark Levy ,  Siva P. Adusumilli

IPC: G02B6/43 ,  G02B6/42

Abstract: Structures that include a distributed Bragg reflector and methods of fabricating a structure that includes a distributed Bragg reflector. The structure includes a substrate, an optical component, and a distributed Bragg reflector positioned between the optical component and the substrate. The distributed Bragg reflector includes airgaps and silicon layers that alternate in a vertical direction with the airgaps to define a plurality of periods.

公开(公告)号：US20220413232A1

公开(公告)日：2022-12-29

申请号：US17362154

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Spencer Porter ,  Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/42

Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.