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    Structures and methods for extraction of device channel width
    1.
    发明授权
    Structures and methods for extraction of device channel width 有权
    用于提取设备通道宽度的结构和方法

    公开(公告)号：US09564375B2

    公开(公告)日：2017-02-07

    申请号：US14054040

    申请日：2013-10-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy Mann ,  Sandeep Puri ,  Sonia Ghosh ,  Anuj Gupta ,  Xusheng Wu

    IPC: G06F17/50 ,  H01L21/66

    CPC classification number: H01L22/14 ,  G01B2210/56 ,  G06F17/5063 ,  G06F17/5068

    Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

    Abstract translation: 公开了用于提取晶体管沟道宽度的方法和设计结构。 实施例可以包括根据晶体管的拉出沟道宽度确定多个集成电路的晶体管的有效沟道宽度，以及基于有效沟道宽度确定目标晶体管的目标沟道宽度。

    Printing minimum width semiconductor features at non-minimum pitch and resulting device
    2.
    发明授权
    Printing minimum width semiconductor features at non-minimum pitch and resulting device 有权
    以非最小间距打印最小宽度的半导体器件，从而产生器件

    公开(公告)号：US09263349B2

    公开(公告)日：2016-02-16

    申请号：US14074981

    申请日：2013-11-08

    Applicant: GLOBALFOUNDRIES inc.

    Inventor： Sonia Ghosh ,  Randy Mann ,  Norman Chen ,  Shaowen Gao

    IPC: G03C5/00 ,  H01L21/66 ,  G06F17/50 ,  H01L21/3213 ,  H01L27/02

    CPC classification number: H01L23/528 ,  G06F17/5068 ,  H01L21/32139 ,  H01L22/12 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/1116 ,  H01L2924/0002 ,  Y02T10/82 ,  H01L2924/00

    Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

    Abstract translation: 公开了形成半导体层的方法，例如金属层，其具有最小宽度特征被隔开大于最小间距的距离，以及所得到的器件。 实施例可以包括确定在半导体层内具有最小宽度的第一形状和第二形状，其中第一形状和第二形状之间的距离大于最小间距，确定第一形状和第二形状之间的中间形状 并且在所述中间形状中指定虚拟形状，其中所述虚拟形状距所述第一形状处于最小间距。

    HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT
    3.
    发明申请
    HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT 有权
    用于静态随机访问存储器（SRAM）布局的HALO / EXTENSION IMPLAN的HARDMASK

    公开(公告)号：US20150091097A1

    公开(公告)日：2015-04-02

    申请号：US14043871

    申请日：2013-10-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xusheng Wu ,  Bingwu Liu ,  Randy Mann

    IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

    CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66803 ,  H01L29/785

    Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

    Abstract translation: 公开了用于提供在半导体器件的静态随机存取存储器（SRAM）布局的晕圈/扩展注入期间使用的硬掩模的方法。 具体地，提供了用于在衬底上形成下拉（PD）晶体管的方法; 在衬底上形成栅极（PG）晶体管; 以及在所述器件上构图硬掩模，所述硬掩模包括与所述PD晶体管相邻的第一部分和与所述PG晶体管相邻的第二部分，其中所述第一部分与所述PD晶体管之间的距离小于所述第二部分与所述PG之间的距离 晶体管。 选择第一部分和PD晶体管以及第二部分和PG晶体管之间的相应距离以防止光晕/延伸注入物撞击PD晶体管的一侧，同时允许光晕/延伸植入物撞击两侧 的PG晶体管。

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