公开(公告)号：US09484300B2

公开(公告)日：2016-11-01

申请号：US14953864

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sonia Ghosh ,  Randy Mann ,  Norman Chen ,  Shaowen Gao

IPC: H01L21/00 ,  H01L23/528 ,  H01L21/66 ,  G06F17/50 ,  H01L21/3213 ,  H01L23/522 ,  H01L27/11 ,  H01L27/02

CPC classification number: H01L23/528 ,  G06F17/5068 ,  H01L21/32139 ,  H01L22/12 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/1116 ,  H01L2924/0002 ,  Y02T10/82 ,  H01L2924/00

Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Abstract translation: 公开了形成半导体层的方法，例如金属层，其具有最小宽度特征被隔开大于最小间距的距离，以及所得到的器件。 实施例可以包括确定在半导体层内具有最小宽度的第一形状和第二形状，其中第一形状和第二形状之间的距离大于最小间距，确定第一形状和第二形状之间的中间形状 并且在所述中间形状中指定虚拟形状，其中所述虚拟形状距所述第一形状处于最小间距。

公开(公告)号：US09443055B2

公开(公告)日：2016-09-13

申请号：US14699705

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Abstract translation: 提供了用于重新定位用于多图案化光刻工艺的电路设计布局和用于制造半导体器件的方法。 在示例性实施例中，提供了一种用于重新定位用于多图案化光刻工艺的电路设计布局的计算机执行方法。 该方法包括分解电路设计布局文件以在计算机中产生分解的布局文件。 每个分解的布局文件与用于多图案化光刻工艺中的相应掩模相关联。 该方法包括通过基于每个选择的分解布局文件特有的光刻限制重新定位所选择的分解布局文件以产生重定向布局文件来在计算机中准备重定向布局文件。 此外，该方法包括在计算机中确定布局文件的组合包括间隔冲突。 该方法还包括通过修改导致间隔冲突的布局文件或布局文件来解决计算机中的间隔冲突。

公开(公告)号：US09064086B2

公开(公告)日：2015-06-23

申请号：US14525833

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract translation: 一种方法包括在计算装置中接收用于集成电路装置的设计布局文件。 设计布局文件指定多个特征的尺寸。 将设计布局文件分解为多个彩色布局文件，每个彩色布局文件在多重图案化处理中表示特定的掩模版。 每个彩色布局文件在计算设备中分别重新定位，以产生多个重定向彩色布局文件。 重新定位每个彩色布局文件包括基于第一多个特征和相邻特征之间的间隔来增加第一多个特征的尺寸。 重新定位的布局文件被组合以生成组合的布局文件。 组合布局文件中的特征在计算装置中重新定位，以基于第二多个特征和相邻特征之间的间隔来增加第二多个特征的尺寸。

公开(公告)号：US09026977B2

公开(公告)日：2015-05-05

申请号：US13968850

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc Tarabbia ,  Norman Chen ,  Jian Liu ,  Nader Magdy Hindawy ,  Tuhin Guha Neogi ,  Mahbub Rashed ,  Anurag Mittal

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/06 ,  G06F2217/78

Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Abstract translation: 一种方法包括将标准单元库的多个单元电连接到电源轨。 沉积接触区以连接多个单元的单元的第一有源区和第二有源区。 第一区域和第二区域位于轨道的相对侧并且电连接到不同的排水沟。 接触区域使用通孔电连接到电源轨。 接触区域被屏蔽以去除接触区域的一部分以将第一活性物质与第二活性区域电分离。

公开(公告)号：US09171735B2

公开(公告)日：2015-10-27

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308 ,  G03F7/00

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US08910094B2

公开(公告)日：2014-12-09

申请号：US13760571

申请日：2013-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract translation: 一种方法包括在计算装置中接收用于集成电路装置的设计布局文件。 设计布局文件指定多个特征的尺寸。 将设计布局文件分解为多个彩色布局文件，每个彩色布局文件在多重图案化处理中表示特定的掩模版。 每个彩色布局文件在计算设备中分别重新定位，以产生多个重定向彩色布局文件。 重新定位每个彩色布局文件包括基于第一多个特征和相邻特征之间的间隔来增加第一多个特征的尺寸。 重新定位的布局文件被组合以生成组合的布局文件。 组合布局文件中的特征在计算装置中被重新定位，以基于第二多个特征和相邻特征之间的间隔来增加第二多个特征的尺寸。

公开(公告)号：US20190101905A1

公开(公告)日：2019-04-04

申请号：US15719680

申请日：2017-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongxin Zhang ,  Shaowen Gao ,  Norman Chen

IPC: G05B19/418

CPC classification number: G05B19/41845 ,  G05B2219/36089 ,  G05B2219/45031

Abstract: Methods according to the disclosure include: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.

公开(公告)号：US20140235055A1

公开(公告)日：2014-08-21

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US10401837B2

公开(公告)日：2019-09-03

申请号：US15719680

申请日：2017-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongxin Zhang ,  Shaowen Gao ,  Norman Chen

IPC: G05B19/418 ,  G06F17/50

Abstract: A method disclosed herein includes: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.

公开(公告)号：US10386715B2

公开(公告)日：2019-08-20

申请号：US15730830

申请日：2017-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Feng Wang ,  Hongxin Zhang ,  Shaowen Gao ,  Norman Chen

IPC: G03F1/36

Abstract: A method of creating an optical proximity correction (OPC) model and assessing the model through optical rule checking (ORC) includes the introduction of post-integration, i.e., post-metallization data. High density critical dimension scanning electron microscopy and backscattered electron scanning electron microscopy from a metallized structure are used during development and verification of the model to accurately predict post-integration behavior.