公开(公告)号：US11056208B1

公开(公告)日：2021-07-06

申请号：US16801728

申请日：2020-02-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Balaji Jayaraman ,  Ramesh Raghavan ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

公开(公告)号：US20250079343A1

公开(公告)日：2025-03-06

申请号：US18240699

申请日：2023-08-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： David Charles Pritchard ,  Ramesh Raghavan ,  Thirunavukkarasu Ranganathan ,  Rajesh Reddy Tummuru ,  Benoit Francois Claude Ramadout ,  Luca Pirro

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.