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公开(公告)号:US20240170575A1
公开(公告)日:2024-05-23
申请号:US18058353
申请日:2022-11-23
发明人: Kiril Biserov Borisov , Mohammed Ahmed Fouad Ibrahim Darwish , Francois C. Weisbuch , Shady Ahmed Abdelwahed Ahmed Elshafie , David Charles Pritchard , Benoit Francois Claude Ramadout
IPC分类号: H01L29/78
CPC分类号: H01L29/7831
摘要: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.
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公开(公告)号:US20240347638A1
公开(公告)日:2024-10-17
申请号:US18301382
申请日:2023-04-17
CPC分类号: H01L29/7851 , H01L21/28123 , H01L29/1037 , H01L29/4983 , H01L29/66545 , H01L29/66795
摘要: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.
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公开(公告)号:US20240274603A1
公开(公告)日:2024-08-15
申请号:US18169304
申请日:2023-02-15
IPC分类号: H01L27/092 , H01L21/762 , H01L21/8238 , H01L23/528 , H01L27/02
CPC分类号: H01L27/092 , H01L21/76224 , H01L21/823878 , H01L23/528 , H01L27/0207
摘要: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.
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