公开(公告)号：US20250079343A1

公开(公告)日：2025-03-06

申请号：US18240699

申请日：2023-08-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： David Charles Pritchard ,  Ramesh Raghavan ,  Thirunavukkarasu Ranganathan ,  Rajesh Reddy Tummuru ,  Benoit Francois Claude Ramadout ,  Luca Pirro

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.

公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

公开(公告)号：US20240274603A1

公开(公告)日：2024-08-15

申请号：US18169304

申请日：2023-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： David Charles Pritchard ,  James P. Mazza ,  Navneet K. Jain ,  Hong Yu

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

公开(公告)号：US20250031439A1

公开(公告)日：2025-01-23

申请号：US18354114

申请日：2023-07-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234

Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.

公开(公告)号：US20240170575A1

公开(公告)日：2024-05-23

申请号：US18058353

申请日：2022-11-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Kiril Biserov Borisov ,  Mohammed Ahmed Fouad Ibrahim Darwish ,  Francois C. Weisbuch ,  Shady Ahmed Abdelwahed Ahmed Elshafie ,  David Charles Pritchard ,  Benoit Francois Claude Ramadout

IPC: H01L29/78

CPC classification number: H01L29/7831

Abstract: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.