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公开(公告)号：US20210036702A1
公开(公告)日：2021-02-04
申请号：US16921571
申请日：2020-07-06
Applicant: Google LLC
Inventor： Houle Gan , Mikhail Popovich , Shuai Jiang , Gregory Sizikov , Chee Yee Chung
IPC: H03K17/687 , G06F1/26
Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
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公开(公告)号：US10905038B1
公开(公告)日：2021-01-26
申请号：US16688384
申请日：2019-11-19
Applicant: Google LLC
Inventor： Federico Pio Centola , Zuowei Shen , Xu Gao , Shawn Emory Bender , Melanie Beauchemin , Mark Villegas , Gregory Sizikov , Chee Yee Chung
IPC: H05K9/00
Abstract: An electromagnetic interference (“EMI”) sheet attenuator includes a planar conductive layer, a first flexible substrate and a second flexible substrate. The first flexible substrate overlies the metal backing layer and including a conductive pattern on a surface of the first flexible substrate. The second flexible substrate overlies the first flexible substrate and also includes the conductive pattern. The conductive pattern on the second flexible substrate is aligned with the conductive pattern on the first flexible substrate.
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公开(公告)号：US10312813B2
公开(公告)日：2019-06-04
申请号：US16170452
申请日：2018-10-25
Applicant: Google LLC
Inventor： Shuai Jiang , Chee Yee Chung , Xin Li
IPC: H02M3/158
Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.
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公开(公告)号：US20190068061A1
公开(公告)日：2019-02-28
申请号：US16170452
申请日：2018-10-25
Applicant: Google LLC
Inventor： Shuai Jiang , Chee Yee Chung , Xin Li
IPC: H02M3/158
Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.
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Patent Agency Ranking
公开(公告)号：US10141849B1
公开(公告)日：2018-11-27
申请号：US15675285
申请日：2017-08-11
Applicant: Google LLC
Inventor： Shuai Jiang , Chee Yee Chung , Xin Li
IPC: H02M3/158
Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.
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公开(公告)号：US20240203630A1
公开(公告)日：2024-06-20
申请号：US18590577
申请日：2024-02-28
Applicant: Google LLC
Inventor： Houle Gan , Shuai Jiang , Gregory Sizikov , Xin Li , Chee Yee Chung
CPC classification number: H01F17/0006 , H05K5/0069
Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.
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公开(公告)号：US11948716B1
公开(公告)日：2024-04-02
申请号：US16800776
申请日：2020-02-25
Applicant: Google LLC
Inventor： Houle Gan , Shuai Jiang , Gregory Sizikov , Xin Li , Chee Yee Chung
CPC classification number: H01F17/0006 , H05K5/0069
Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.
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公开(公告)号：US11552634B2
公开(公告)日：2023-01-10
申请号：US16921571
申请日：2020-07-06
Applicant: Google LLC
Inventor： Houle Gan , Mikhail Popovich , Shuai Jiang , Gregory Sizikov , Chee Yee Chung
IPC: H03K17/68 , H03K17/687 , G06F1/26 , H02M3/07
Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
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公开(公告)号：US10742211B1
公开(公告)日：2020-08-11
申请号：US16527569
申请日：2019-07-31
Applicant: Google LLC
Inventor： Houle Gan , Mikhail Popovich , Shuai Jiang , Gregory Sizikov , Chee Yee Chung
IPC: H01L25/00 , H03K17/687 , G06F1/26 , H02M3/07
Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
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