公开(公告)号：US5933158A

公开(公告)日：1999-08-03

申请号：US926426

申请日：1997-09-09

申请人： Gregory N. Santos ,  Robert C. Elliott

发明人： Gregory N. Santos ,  Robert C. Elliott

IPC分类号： G06F12/08 ,  G06F3/14 ,  G06F12/10 ,  G06F13/36 ,  G06T11/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G06F12/06

CPC分类号： G09G5/39 ,  G06F12/1027 ,  G06F12/1081 ,  G06F3/14 ,  G09G2360/121 ,  G09G2360/125 ,  G09G5/363

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向计算机系统物理存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联的图形数据页面的特征标志 。 其中一个特征标志被用作每个GART表条目的链接位，使得当核心逻辑芯片组读取存储在系统存储器中的GART表条目中的所选择的一个时，它将所选择的一个存储在其高速缓冲存储器中 并确定其链路位是否被设置。 如果所选择的第一个的链接位被设置，则所选择的一个的下一个被存储在高速缓冲存储器中，并且如果其链接位被设置，则所选择的一个的后续的一个被存储在高速缓冲存储器 直到其中一个链接位被确定为不被设置。

公开(公告)号：US5914730A

公开(公告)日：1999-06-22

申请号：US926421

申请日：1997-09-09

申请人： Gregory N. Santos ,  Robert C. Elliott

发明人： Gregory N. Santos ,  Robert C. Elliott

IPC分类号： G06F12/08 ,  G06F3/14 ,  G06F12/10 ,  G06F13/36 ,  G06T11/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G06F13/16

CPC分类号： G06F3/14 ,  G06F12/1081 ,  G09G5/39 ,  G06F12/1027 ,  G09G2360/121 ,  G09G2360/125 ,  G09G5/363

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。 核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。 GART缓存条目控制寄存器由应用程序编程接口（如GART微型端口驱动程序）用于向核心逻辑芯片组指出芯片组缓存中的单个GART表条目应无效和/或更新。 核心逻辑芯片组然后可以对单独的GART表条目执行所需的无效和/或更新操作，而不必刷新或以其它方式干扰存储在高速缓存中的其他仍然相关的GART表条目。

公开(公告)号：US5999198A

公开(公告)日：1999-12-07

申请号：US925772

申请日：1997-09-09

申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC分类号： G06F3/14 ,  G06F12/08 ,  G09G5/393 ,  G06F15/16

CPC分类号： G06F3/14 ,  G06F12/0875 ,  G09G5/393 ,  G09G2360/121

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

公开(公告)号：US5990914A

公开(公告)日：1999-11-23

申请号：US926425

申请日：1997-09-09

申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC分类号： G06F3/14 ,  G06F11/07 ,  G06F13/16

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0745 ,  G06F3/14

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。 其中一个功能标志用作相应存储器页面的当前位。 当特征标志当前位被设置时，存储器页面已被保留在用于图形数据的物理存储器中，并且可以执行地址转换。 当特征标志当前位清除时，存储器页面尚未被保留用于物理存储器中的图形数据，然后必须确定是否执行转换或者向计算机处理器生成错误信号。

公开(公告)号：US5936640A

公开(公告)日：1999-08-10

申请号：US941862

申请日：1997-09-30

申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC分类号： G06F3/14 ,  G06F12/10 ,  G06F15/00 ,  G06F12/06

CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F12/1081

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 多个AGP存储器映射状态和控制寄存器存储在计算机系统存储器中，用于计算机系统中AGP功能的状态和控制。

公开(公告)号：US5914727A

公开(公告)日：1999-06-22

申请号：US925773

申请日：1997-09-09

申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC分类号： G06F12/02 ,  G06F12/10 ,  H04N7/26 ,  H04N7/50 ,  G06F15/16

CPC分类号： G06F12/1081 ,  G06F12/0292 ,  H04N19/423 ,  H04N19/61

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。 从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址 启动或POST。 AGP有效位设置为指示AGP设备是否存在。 如果AGP设备不存在，则在计算机系统启动期间不会分配虚拟内存地址空间。

公开(公告)号：US20140036966A1

公开(公告)日：2014-02-06

申请号：US13563036

申请日：2012-07-31

申请人： Robert C. Elliott

发明人： Robert C. Elliott

IPC分类号： H04B1/707

CPC分类号： H04B1/69 ,  H04Q2213/13216

摘要： Varying insertion rates of deletable characters that are discarded by a receiver, as a function of transmission rate in spread spectrum clocking systems. Such systems can generate a spread spectrum modulation, based on their knowledge about the rate of transmission. The systems can dynamically adjust the rate/numbers of deletable characters that are inserted in the transmission. Accordingly, the insertion rate can increase (or decrease) when the transmission rate exceeds above (or falls below) a predetermined threshold.

摘要翻译： 由扩展频谱计时系统作为传输速率的函数，由接收机丢弃的可删除字符的插入率不同。 这样的系统可以基于他们关于传输速率的知识来生成扩频调制。 系统可以动态地调整插入到传输中的可删除字符的速率/数量。 因此，当传输速率超过预定阈值（或低于）时，插入速率可以增加（或减小）。

公开(公告)号：US08495757B2

公开(公告)日：2013-07-23

申请号：US12765041

申请日：2010-04-22

申请人： Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

发明人： Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

IPC分类号： G06F21/02

CPC分类号： G06F21/78 ,  G06F21/6209 ,  G06F21/74 ,  G06F2221/2101 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2147 ,  G06F2221/2149

摘要： A system and method is disclosed for placing an electronic apparatus into a protected state in response to environmental data. The method discloses: receiving a set of environmental data applicable to an electronic apparatus; generating an environmental status applicable to the electronic apparatus based-on the environmental data; and placing the electronic apparatus into a protected state based-on the environmental status. The system discloses an environment characterization module which receives a set of environmental data applicable to an electronic apparatus, and generates an environmental status applicable to the electronic apparatus based-on the environmental data; and an apparatus protection module which places the electronic apparatus into a protected state based-on the environmental status.

摘要翻译： 公开了一种用于响应于环境数据将电子设备置于受保护状态的系统和方法。 该方法公开：接收适用于电子设备的一组环境数据; 基于环境数据产生适用于电子设备的环境状态; 并且基于环境状态将电子设备置于受保护状态。 该系统公开了一种环境表征模块，其接收可应用于电子设备的一组环境数据，并且基于环境数据生成可应用于电子设备的环境状态; 以及基于环境状态将电子设备置于受保护状态的设备保护模块。

公开(公告)号：US07340551B2

公开(公告)日：2008-03-04

申请号：US11274607

申请日：2005-11-15

申请人： Robert C. Elliott ,  Hubert E. Brinkmann, Jr.

发明人： Robert C. Elliott ,  Hubert E. Brinkmann, Jr.

IPC分类号： G06F13/36

CPC分类号： G06F13/4022 ,  G06F3/0601 ,  G06F2003/0692

摘要： A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from or provided to the storage drive.

摘要翻译： 桥接器包括到多个主机的接口，到单端口存储驱动器和仲裁逻辑的接口。 仲裁逻辑控制和允许主机同时访问单端口存储驱动器，使得该桥不需要存储从存储驱动器接收或提供给存储驱动器的读或写数据。

公开(公告)号：US07295513B2

公开(公告)日：2007-11-13

申请号：US10669151

申请日：2003-09-23

申请人： Robert C. Elliott ,  Witold A. Krzymien

发明人： Robert C. Elliott ,  Witold A. Krzymien

IPC分类号： G01R31/08 ,  G06F11/00 ,  G08C15/00

CPC分类号： H04W72/1226 ,  H04L12/1881 ,  H04L12/189 ,  H04W72/1247

摘要： A method for scheduling packet data transmissions in a wireless communication system is described wherein a priority function is based on a channel state indicator (CSI), the projected average throughput of the users, and a tuning parameter designed to control the throughput and fairness characteristics of the scheduling algorithm. The method also considers fairness criteria dictated by predetermined Quality of Service (QoS) requirements. The channel state indicator may be a Requested Data Rate (RDR) or Carrier-to-Interference ratio (C/I) information. The base station calculates a priority function for the multiple mobile users. Each priority function is a function of the CSI, the projected average throughput of a given mobile user, the average projected throughput over a set of users, and the tuning parameter.

摘要翻译： 描述了一种用于在无线通信系统中调度分组数据传输的方法，其中优先级功能基于信道状态指示符（CSI），用户的预计平均吞吐量以及调整参数，该调整参数旨在控制吞吐量和公平性 调度算法。 该方法还考虑了由预定的服务质量（QoS）要求所规定的公平性标准。 信道状态指示符可以是请求数据速率（RDR）或载波干扰比（C / I）信息。 基站计算多个移动用户的优先级功能。 每个优先级功能是CSI的功能，给定移动用户的预计平均吞吐量，一组用户的平均预计吞吐量以及调谐参数。