公开(公告)号：US07295513B2

公开(公告)日：2007-11-13

申请号：US10669151

申请日：2003-09-23

Applicant: Robert C. Elliott ,  Witold A. Krzymien

Inventor： Robert C. Elliott ,  Witold A. Krzymien

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00

CPC classification number: H04W72/1226 ,  H04L12/1881 ,  H04L12/189 ,  H04W72/1247

Abstract: A method for scheduling packet data transmissions in a wireless communication system is described wherein a priority function is based on a channel state indicator (CSI), the projected average throughput of the users, and a tuning parameter designed to control the throughput and fairness characteristics of the scheduling algorithm. The method also considers fairness criteria dictated by predetermined Quality of Service (QoS) requirements. The channel state indicator may be a Requested Data Rate (RDR) or Carrier-to-Interference ratio (C/I) information. The base station calculates a priority function for the multiple mobile users. Each priority function is a function of the CSI, the projected average throughput of a given mobile user, the average projected throughput over a set of users, and the tuning parameter.

Abstract translation: 描述了一种用于在无线通信系统中调度分组数据传输的方法，其中优先级功能基于信道状态指示符（CSI），用户的预计平均吞吐量以及调整参数，该调整参数旨在控制吞吐量和公平性 调度算法。 该方法还考虑了由预定的服务质量（QoS）要求所规定的公平性标准。 信道状态指示符可以是请求数据速率（RDR）或载波干扰比（C / I）信息。 基站计算多个移动用户的优先级功能。 每个优先级功能是CSI的功能，给定移动用户的预计平均吞吐量，一组用户的平均预计吞吐量以及调谐参数。

公开(公告)号：US06070215A

公开(公告)日：2000-05-30

申请号：US42326

申请日：1998-03-13

Applicant: Todd J. Deschepper ,  Robert C. Elliott

Inventor： Todd J. Deschepper ,  Robert C. Elliott

IPC: G06F1/32 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F1/3203 ,  G06F13/4031

Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine. The computer system may also include a laptop computer docked to an expansion base with a South bridge included in the computer and the expansion base.

Abstract translation: 计算机系统包括南桥逻辑器件，其监视FLUSHREQ信号和当CPU将计算机转换到低功耗操作模式时信号的掩码。 一旦屏蔽，FLUSHREQ不能被断言到北桥，并且避免CPU和ISA设备在PCI总线上运行周期的冲突。 南桥还屏蔽了PCI总线上运行不是由CPU发起的周期的所有请求。 南桥包括一个可编程控制寄存器和一个PCI仲裁器。 当寄存器中设置了一个控制位时，PCI仲裁器等待FLUSHREQ被取消置位，然后屏蔽FLUSHREQ。 PCI仲裁器也优选地通过屏蔽所有非CPU来禁用PCI仲裁。 当非CPU请求被屏蔽时，只有CPU可以运行PCI周期。 可编程控制寄存器还包括当FLUSHREQ和非CPU请求信号被请求掩码状态机屏蔽时设置的屏蔽状态位。 计算机系统还可以包括与包括在计算机中的南桥和扩展基座对接的扩展基座的膝上型计算机。

公开(公告)号：US5999198A

公开(公告)日：1999-12-07

申请号：US925772

申请日：1997-09-09

Applicant: Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

Inventor： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC: G06F3/14 ,  G06F12/08 ,  G09G5/393 ,  G06F15/16

CPC classification number: G06F3/14 ,  G06F12/0875 ,  G09G5/393 ,  G09G2360/121

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract translation: 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

公开(公告)号：US5539386A

公开(公告)日：1996-07-23

申请号：US206972

申请日：1994-03-07

Applicant: Robert C. Elliott

Inventor： Robert C. Elliott

IPC: G01N21/41 ,  G08B17/103

CPC classification number: G01N21/41 ,  Y10S128/13

Abstract: A non-intrusive optical transmission liquid monitoring system that detects bubbles in a transparent liquid flowing through a transparent tubing. The system dynamically compensates for changes in optical transmission efficiency of the monitored liquid and distinguishes between the transition from liquid to air and air to liquid. A system comprising a light transmitter and a light sensitive receiver secured on opposite sides of a transparent tubing. The output of the receiver is fed into a self-referencing and drift compensation circuit. The integrated output is connected to circuitry sensitive to a change in the integrated output and triggers one of two possible alarms to indicate a detected transition from liquid to air, or air to liquid.

Abstract translation: 一种非侵入式透光液体监测系统，用于检测流过透明管道的透明液体中的气泡。 系统动态地补偿被监测液体的光传输效率的变化，并区分从液体到空气和空气到液体的过渡。 一种包括光传输器和固定在透明管道的相对侧上的光敏接收器的系统。 接收机的输出馈入自参考和漂移补偿电路。 集成输出连接到对集成输出变化敏感的电路，并触发两个可能的报警之一，以指示从液体到空气或空气到液体的检测过渡。

公开(公告)号：US20110265191A1

公开(公告)日：2011-10-27

申请号：US12765041

申请日：2010-04-22

Applicant: Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

Inventor： Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

IPC: G06F21/02

CPC classification number: G06F21/78 ,  G06F21/6209 ,  G06F21/74 ,  G06F2221/2101 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2147 ,  G06F2221/2149

Abstract: A system and method is disclosed for placing an electronic apparatus into a protected state in response to environmental data. The method discloses: receiving a set of environmental data applicable to an electronic apparatus; generating an environmental status applicable to the electronic apparatus based-on the environmental data; and placing the electronic apparatus into a protected state based-on the environmental status. The system discloses an environment characterization module which receives a set of environmental data applicable to an electronic apparatus, and generates an environmental status applicable to the electronic apparatus based-on the environmental data; and an apparatus protection module which places the electronic apparatus into a protected state based-on the environmental status.

Abstract translation: 公开了一种用于响应于环境数据将电子设备置于受保护状态的系统和方法。 该方法公开：接收适用于电子设备的一组环境数据; 基于环境数据产生适用于电子设备的环境状态; 并且基于环境状态将电子设备置于受保护状态。 该系统公开了一种环境表征模块，其接收可应用于电子设备的一组环境数据，并且基于环境数据生成可应用于电子设备的环境状态; 以及基于环境状态将电子设备置于受保护状态的设备保护模块。

公开(公告)号：US06675244B1

公开(公告)日：2004-01-06

申请号：US09507000

申请日：2000-02-18

Applicant: Robert C. Elliott ,  William C. Galloway

Inventor： Robert C. Elliott ,  William C. Galloway

IPC: G06F1316

CPC classification number: G06F13/405

Abstract: The method of the present invention enables a SCSI repeater to dynamically determine the speed of an input device and adjust the repeater's output speed accordingly. Thus, the SCSI repeater can transparently connect independent SCSI buses that are connected to different devices with different requirements, preventing the slowest device from limiting the speed of the fastest device.

Abstract translation: 本发明的方法使得SCSI中继器能够动态地确定输入设备的速度并相应地调整中继器的输出速度。 因此，SCSI中继器可以透明地连接连接到具有不同要求的不同设备的独立SCSI总线，从而防止最慢的设备限制最快设备的速度。

公开(公告)号：US5838993A

公开(公告)日：1998-11-17

申请号：US639879

申请日：1996-04-26

Applicant: Dwight D. Riley ,  Robert C. Elliott

Inventor： Dwight D. Riley ,  Robert C. Elliott

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/20

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

Abstract translation: 分布式直接存储器访问（DMA）架构，其中DMA控制器被修改以创建隔离的DMA通道。 每个隔离通道都包括其自己的一组唯一可寻址寄存器，提供与常规DMA控制器的功能兼容性。 DMA主机与计算机系统兼容交互，并将特殊周期透明地传送到隔离的DMA通道，以使分布式DMA架构显示为DMA控制器。 DMA主机为隔离通道产生特殊周期，以共享具有多个通道的通用写入数据，并将读取数据合并到单个DMA控制器兼容寄存器中。 通道4级联也通过跟踪寄存器和特殊周期来处理，以保持通道4的禁用和屏蔽功能，因为它影响通道0-3。

公开(公告)号：US20140036966A1

公开(公告)日：2014-02-06

申请号：US13563036

申请日：2012-07-31

Applicant: Robert C. Elliott

Inventor： Robert C. Elliott

IPC: H04B1/707

CPC classification number: H04B1/69 ,  H04Q2213/13216

Abstract: Varying insertion rates of deletable characters that are discarded by a receiver, as a function of transmission rate in spread spectrum clocking systems. Such systems can generate a spread spectrum modulation, based on their knowledge about the rate of transmission. The systems can dynamically adjust the rate/numbers of deletable characters that are inserted in the transmission. Accordingly, the insertion rate can increase (or decrease) when the transmission rate exceeds above (or falls below) a predetermined threshold.

Abstract translation: 由扩展频谱计时系统作为传输速率的函数，由接收机丢弃的可删除字符的插入率不同。 这样的系统可以基于他们关于传输速率的知识来生成扩频调制。 系统可以动态地调整插入到传输中的可删除字符的速率/数量。 因此，当传输速率超过预定阈值（或低于）时，插入速率可以增加（或减小）。

公开(公告)号：US08495757B2

公开(公告)日：2013-07-23

申请号：US12765041

申请日：2010-04-22

Applicant: Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

Inventor： Leonard E. Russo ,  Walter A. Gaspard ,  Jeff W. Wolford ,  Richard J. Tomaszewski ,  Robert C. Elliott

IPC: G06F21/02

CPC classification number: G06F21/78 ,  G06F21/6209 ,  G06F21/74 ,  G06F2221/2101 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2147 ,  G06F2221/2149

Abstract: A system and method is disclosed for placing an electronic apparatus into a protected state in response to environmental data. The method discloses: receiving a set of environmental data applicable to an electronic apparatus; generating an environmental status applicable to the electronic apparatus based-on the environmental data; and placing the electronic apparatus into a protected state based-on the environmental status. The system discloses an environment characterization module which receives a set of environmental data applicable to an electronic apparatus, and generates an environmental status applicable to the electronic apparatus based-on the environmental data; and an apparatus protection module which places the electronic apparatus into a protected state based-on the environmental status.

Abstract translation: 公开了一种用于响应于环境数据将电子设备置于受保护状态的系统和方法。 该方法公开：接收适用于电子设备的一组环境数据; 基于环境数据产生适用于电子设备的环境状态; 并且基于环境状态将电子设备置于受保护状态。 该系统公开了一种环境表征模块，其接收可应用于电子设备的一组环境数据，并且基于环境数据生成可应用于电子设备的环境状态; 以及基于环境状态将电子设备置于受保护状态的设备保护模块。

公开(公告)号：US07340551B2

公开(公告)日：2008-03-04

申请号：US11274607

申请日：2005-11-15

Applicant: Robert C. Elliott ,  Hubert E. Brinkmann, Jr.

Inventor： Robert C. Elliott ,  Hubert E. Brinkmann, Jr.

IPC: G06F13/36

CPC classification number: G06F13/4022 ,  G06F3/0601 ,  G06F2003/0692

Abstract: A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from or provided to the storage drive.

Abstract translation: 桥接器包括到多个主机的接口，到单端口存储驱动器和仲裁逻辑的接口。 仲裁逻辑控制和允许主机同时访问单端口存储驱动器，使得该桥不需要存储从存储驱动器接收或提供给存储驱动器的读或写数据。