公开(公告)号：US5809024A

公开(公告)日：1998-09-15

申请号：US679668

申请日：1996-07-12

申请人： H. Earl Ferguson ,  Jeff Prince ,  Randy Ryals ,  Gururaj Singh ,  Michael Yip

发明人： H. Earl Ferguson ,  Jeff Prince ,  Randy Ryals ,  Gururaj Singh ,  Michael Yip

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5614

摘要： In a segmentation and reassembly module in a local area network switch module, a method and apparatus for storing fixed length data cells received from an ATM network in a plurality of memory buffers during the reassembly of the data cells in to a variable length data packet to be transmitted on an attached local area network.

摘要翻译： 在局域网交换机模块中的分段和重组模块中，一种方法和装置，用于在将数据小区重新组装成可变长度数据分组期间存储从多个存储器缓冲器中的ATM网络接收的固定长度数据单元， 在附加的局域网上传输。

公开(公告)号：US06272133B1

公开(公告)日：2001-08-07

申请号：US09315769

申请日：1999-05-20

申请人： Jan Bialkowski ,  Gururaj Singh

发明人： Jan Bialkowski ,  Gururaj Singh

IPC分类号： H04L1228

CPC分类号： H04L47/10 ,  H04L47/2441

摘要： A method of filtering packets having a class. The method includes the steps of accessing a table comprised of entries that include an indication to which class a given entry applies. Then there is the step of searching the entries until an entry whose class indication corresponds to a current class of the packet. Next there is the step of forwarding a frame associated with the entry whose class indication corresponds to the class of the packet. A data communication apparatus. The apparatus includes a mechanism for routing or switching packets. The apparatus includes a memory having information for routing or switching the packets. The apparatus includes a mechanism for compaction of information in the memory which removes redundancies in the information.

摘要翻译： 一种过滤具有类的数据包的方法。 该方法包括以下步骤：访问由包括给定条目应用于哪个类别的指示的条目组成的表。 然后，搜索条目直到其类别指示对应于分组的当前类的条目为止。 接下来，转发与类别指示对应于分组的类别的条目相关联的帧。 数据通信装置。 该装置包括用于路由或切换分组的机制。 该装置包括具有用于路由或切换分组的信息的存储器。 该装置包括用于压缩存储器中的信息的机制，其消除信息中的冗余。

公开(公告)号：US5852601A

公开(公告)日：1998-12-22

申请号：US870755

申请日：1997-06-09

申请人： Peter Newman ,  Willie T. Glover ,  Gururaj Singh ,  Amar Gupta ,  Clifford James Buckley

发明人： Peter Newman ,  Willie T. Glover ,  Gururaj Singh ,  Amar Gupta ,  Clifford James Buckley

IPC分类号： H04L12/56 ,  H04J3/14 ,  H04J3/26

CPC分类号： H04L12/5602 ,  H04L2012/5635

摘要： Reactive congestion control in an asynchronous transfer mode (ATM) network where the network is formed by the interconnection of nodes each including a forward path for transfer of information from source to destination through the network and a return path for returning congestion control signals. Each source includes a modifiable issue rate unit which issues forward information signals at different rates for virtual channels in response to the presence and absence of congestion signals received on the return path.

摘要翻译： 异步传输模式（ATM）网络中的无效拥塞控制，其中网络由每个节点的互连形成，每个节点包括用于通过网络从源到目的地传送信息的前向路径和用于返回拥塞控制信号的返回路径。 每个源包括可修改的发布率单元，其响应于在返回路径上接收到的拥塞信号的存在和不存在，针对虚拟信道以不同的速率发出前向信息信号。

公开(公告)号：US5119374A

公开(公告)日：1992-06-02

申请号：US769755

申请日：1991-10-03

申请人： Farzin Firoozmand ,  Gururaj Singh

发明人： Farzin Firoozmand ,  Gururaj Singh

IPC分类号： H04L12/433

CPC分类号： H04L12/433

摘要： The standard FDDI priority algorithm is implemented by programming Token Holding Time (THT) threshold values for asynchronous service either in an increasing or decreasing order as a function of token holding time. If the thresholds are programmed in a decreasing order, all higher priority data is sent to the network before any lower priority data is sent. If the thresholds are programmed in an increasing order, highest priority data is sent first, until the unexpired token holding time falls below the threshold value for that priority; the next lower priority level data then is transmitted, and so on. Accordingly, at least some data of all priority assignments pending for transmission are sent to the medium during each token capture.

摘要翻译： 标准FDDI优先级算法是通过根据令牌保持时间以递增或递减的顺序编程异步服务的令牌保持时间（THT）阈值来实现的。 如果阈值以递减顺序编程，则在发送任何较低优先级数据之前，将所有较高优先级的数据发送到网络。 如果以增加的顺序编程阈值，则首先发送最高优先级数据，直到未到期的令牌保持时间低于该优先级的阈值为止; 然后发送下一个较低优先级数据，依此类推。 因此，在每个令牌捕获期间，待发送的所有优先级分配的至少一些数据被发送到介质。

公开(公告)号：US5379297A

公开(公告)日：1995-01-03

申请号：US866317

申请日：1992-04-09

申请人： Willie T. Glover ,  Gururaj Singh ,  Amar Gupta ,  Peter Newman

发明人： Willie T. Glover ,  Gururaj Singh ,  Amar Gupta ,  Peter Newman

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J3/16

CPC分类号： H04L12/5602 ,  H04L49/1553 ,  H04Q11/0478 ,  H04L2012/563 ,  H04L2012/5632 ,  H04L2012/5635 ,  H04L2012/5636 ,  H04L2012/5637

摘要： A communication unit for concurrently processing cells in an asynchronous transfer mode (ATM) network. Packets are segmented into a plurality of cells concurrently for a plurality of channels for transmission over the (ATM) network. Cells received from the ATM network are reassembled concurrently for the plurality of channels. Pipelined processing units are employed for segmentation and for reassembly each having logic control, control memory, and data memory. The segmentation unit control memory stores two-dimensional queues with first dimension rate queues for queueing descriptors for cells of different channels having cells to be transmitted and with second dimension channel queues for each channel having a cell descriptor in the rate queue.

摘要翻译： 一种用于在异步传输模式（ATM）网络中同时处理小区的通信单元。 分组被同时分割成多个小区用于多个信道用于在（ATM）网络上传输。 从ATM网络接收的小区对于多个信道重新组合。 流水线处理单元用于分段和重组，每个具有逻辑控制，控制存储器和数据存储器。 分段单元控制存储器存储具有第一尺寸速率队列的二维队列，用于排列具有要发送的小区的不同信道的小区的描述符，并且对于具有在速率队列中的小区描述符的每个信道，具有第二维度信道队列。

公开(公告)号：US4718057A

公开(公告)日：1988-01-05

申请号：US771339

申请日：1985-08-30

申请人： P. Venkitakrishnan ,  Gururaj Singh ,  Ronald C. Laugesen

发明人： P. Venkitakrishnan ,  Gururaj Singh ,  Ronald C. Laugesen

IPC分类号： H04Q3/42 ,  G06F15/78 ,  G06F17/10 ,  H04M1/253 ,  H04Q1/457 ,  H04Q11/04 ,  H04J1/10 ,  H04J3/02

CPC分类号： G06F15/7832 ,  H04M1/253 ,  H04Q1/4575 ,  H04Q11/0428 ,  H04Q2213/13034 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/1319 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13396 ,  H04Q2213/13405

摘要： An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.

摘要翻译： 公开了一种全数字信号处理器（DSP），其对于接收和发送的信号以及其他功能执行脉冲编码调制（PCM）编码和解码（CODEC）滤波操作。 用户可以通过微处理器访问各种可编程寄存器，以指定由DSP执行程序所使用的参数。 提供两个19位宽的双向数据总线用于各种元件之间的时分多路复用通信，其中包括随机存取存储器（RAM），算术逻辑单元（ALU）以及与接收端模拟到 数字（A / D）转换器和发射侧数模（D / A）转换器。 编程逻辑阵列（PLA）执行控制ALU部分处理信号的微码。 可以在PLA的控制下进行各种其他操作，例如通信中常用的双音多频（DTMF）信号的产生。 DSP的架构提供了许多用户可访问的寄存器，用于存储在DTMEC信号生成中使用的参数和系数，在CODEC滤波以及信号的压缩和扩展中。 通用DSP的设计很容易扩展，以容纳并行处理的附加电路元件和/或更多信号。