公开(公告)号：US20240362022A1

公开(公告)日：2024-10-31

申请号：US18309203

申请日：2023-04-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  KAIWEN CAO ,  ADITYA DHAKAL

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3005 ,  G06F9/3877

Abstract: Systems and methods are provided for a dynamic communication architecture that can include decentralized heterogenous accelerators, and an operation of mapping corresponding decentralized virtualized accelerators. The mapping of corresponding decentralized virtualized accelerators is performed on top of, for example, a memory-mapped multi-accelerator communication architecture to enable effective and flexible sharing of data. The mapping can be dynamically adjusted with regard to the workload running by analyzing workflow communication.

公开(公告)号：US20220291952A1

公开(公告)日：2022-09-15

申请号：US17198871

申请日：2021-03-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US20240303078A1

公开(公告)日：2024-09-12

申请号：US18181307

申请日：2023-03-09

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  KIRK M. BRESNIKER

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/5016

Abstract: The disclosure provides for systems and methods for improving bandwidth and latency associated with executing data requests in disaggregated memory by leveraging usage indicators (also referred to as usage value), such as “freshness” of data operators and processing “gravity” of near memory compute functions. Examples of the systems and methods disclosed herein generate data operators comprising near memory compute functions offloaded proximate to disaggregated memory nodes, assign a usage value to each data operator based on at least one of: (i) a freshness indicator for each data operators, and (ii) a gravity indicator for each near memory compute function; and allocate data operations to the data operators based on the usage value.

公开(公告)号：US20240036938A1

公开(公告)日：2024-02-01

申请号：US17876450

申请日：2022-07-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  DUNCAN ROWETH ,  DEREK SCHUMACHER

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/5083 ,  G06F9/542

Abstract: Systems and methods are provided for a modular switch system that comprises disaggregated components, plugins, and managers that enable flexibility to adjust the dynamic configuration of a switch system. This can create modularity and customizability at different times of the lifecycle of the currently configured switch system.

公开(公告)号：US20240338132A1

公开(公告)日：2024-10-10

申请号：US18296197

申请日：2023-04-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： KIRK M. BRESNIKER ,  DEJAN S. MILOJICIC

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/067

Abstract: The disclosure includes a system and methods provide for optimizing performance of disaggregated memory architectures in terms of time and energy. Examples of the systems and methods disclosed herein provide for a near memory compute proximate to a disaggregated memory that can be implemented to receive, from a compute node, one or more requests to perform computation functions on data stored at the disaggregated memory and collect telemetry data for the disaggregated memory, a near memory compute proximate to the disaggregated memory, and the compute node. The systems and methods disclosed herein can also model a plurality of configurations for executing the one or more requests based on the telemetry data, select a modeled configuration of the plurality of modeled configurations for executing the one or more requests, and assign one or more of a plurality of data operators of the near memory compute according to the selected modeled configuration.

公开(公告)号：US20190319838A1

公开(公告)日：2019-10-17

申请号：US15955657

申请日：2018-04-17

Applicant: Hewlett Packard Enterprise Development LP

Inventor： DEJAN S. MILOJICIC

IPC: H04L12/24 ,  G06F9/50 ,  G06F12/14

Abstract: Systems and methods for system reconfiguration of a computing system that includes a plurality of memory and computing resources, may include: assigning a reconfiguration capability to a user, the reconfiguration capability granting the user a right to reconfigure at least one of memory and computing resources in the computing system; a controller of the computing system receiving a reconfiguration request from a user for a requested system reconfiguration along with that user's configuration capability; the controller of the computing system verifying that the user from which the reconfiguration request was received has the rights to make the requested system reconfiguration; and the controller of the system executing the requested system reconfiguration if the user has the rights to make the requested system reconfiguration.

公开(公告)号：US20240362031A1

公开(公告)日：2024-10-31

申请号：US18308275

申请日：2023-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  Sai Rahul Chalamalasetti ,  Sergey Serebryakov

IPC: G06F9/445 ,  G06F11/34

CPC classification number: G06F9/44505 ,  G06F11/3495

Abstract: Systems and methods are provided for an accelerator system that includes a baseline (production) accelerator, optimizing accelerator, and control hardware accelerator, and an operation of alternatingly switching the production/optimizing accelerators between production and optimizing. With two production/optimizing accelerators, at any given point in time, one accelerator adapts while another accelerator processes data. Once the second accelerator starts doing a better job (e.g., has adapted to data drift), the accelerators change their modes, and the trainable accelerator becomes the “optimized” one. The accelerators do this non-stop, thus maintaining redundancy, providing expected quality of service (QOS) and adapting to data/concept drift.

公开(公告)号：US20240362000A1

公开(公告)日：2024-10-31

申请号：US18308570

申请日：2023-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  ADITYA DHAKAL ,  EITAN FRACHTENBERG ,  NINAD SANJAY HOGADE ,  ROLANDO PABLO HONG ENRIQUES ,  GOURAV RATTIHALLI ,  TOBIAS PFANDZELTER

IPC: G06F8/41 ,  G06F9/48 ,  G06N5/022

CPC classification number: G06F8/447 ,  G06F9/4881 ,  G06N5/022

Abstract: Systems and methods are provided for implementing an iterative function deployment in a Function-as-a-Service (FaaS) computing environment. For example, the system may receive a request to execute a program and convert machine-readable code from the request into functions that are deployable in the FaaS computing environment. The system may determine a first deployment of the functions that defines scheduling and execution tasks, and also an execution metric by a trained prediction model. The system may adjust execution of the plurality of functions and also adjust the execution metric in a second deployment. The system may implement the second deployment at run-time, such that the machine-readable code from the request is executed by the computing components of the FaaS infrastructure in accordance with the second deployment.

公开(公告)号：US20240045726A1

公开(公告)日：2024-02-08

申请号：US17875273

申请日：2022-07-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： KENNETH LEACH ,  DEJAN S. MILOJICIC ,  MAXIM ALT

IPC: G06F9/50

CPC classification number: G06F9/505

Abstract: Systems and methods are provided for maintaining a desired efficiency of use of resources in a computing system, such as a high performance computing (HPC) system in conjunction with a desired quality of service (QoS) associated with performance of an application executed by the resources. Efficiency and QoS may be considered together, and the provided systems and methods optimize both during application runtime.

公开(公告)号：US20220138204A1

公开(公告)日：2022-05-05

申请号：US17085805

申请日：2020-10-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CATHERINE GRAVES ,  CAN LI ,  JOHN PAUL STRACHAN ,  DEJAN S. MILOJICIC ,  KIMBERLY KEETON

IPC: G06F16/2455 ,  G06F16/22 ,  G06F16/901 ,  G06F1/3296 ,  G06F1/3206 ,  G11C27/00 ,  G11C13/00

Abstract: Encoding of domain logic rules in an analog content addressable memory (aCAM) is disclosed. By encoding domain logic in an aCAM, rapid and flexible search capabilities are enabled, including the capability to search ranges of analog values, fuzzy match capabilities, and optimized parameter search capabilities. This is achieved with low latency by using only a small number of clock cycles at low power. A domain logic ruleset may be represented using various data structures such as decision trees, directed graphs, or the like. These representations can be converted to a table of values, where each table column can be directly mapped to a corresponding row of the aCAM.