公开(公告)号：US20230156380A1

公开(公告)日：2023-05-18

申请号：US18154580

申请日：2023-01-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04Q11/00 ,  H04L49/15 ,  H04L49/00 ,  H04L49/45

CPC classification number: H04Q11/0005 ,  H04L49/15 ,  H04L49/30 ,  H04L49/45 ,  H04Q2011/0041 ,  H04Q2011/0052

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

公开(公告)号：US11558682B2

公开(公告)日：2023-01-17

申请号：US17048850

申请日：2018-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04Q11/00 ,  H04L49/15 ,  H04L49/00 ,  H04L49/45

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

公开(公告)号：US20180217929A1

公开(公告)日：2018-08-02

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0607 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US20170185343A1

公开(公告)日：2017-06-29

申请号：US15314710

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

公开(公告)号：US20210337286A1

公开(公告)日：2021-10-28

申请号：US17048850

申请日：2018-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04Q11/00 ,  H04L12/933 ,  H04L12/935 ,  H04L12/931

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

公开(公告)号：US20210167992A1

公开(公告)日：2021-06-03

申请号：US17047833

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04L12/42 ,  H04L12/403 ,  H04L12/24

Abstract: A co-packaged, multiplane network includes: an enclosure; a portion of a first network plane disposed within the enclosure and comprising a first plurality of interconnected switches; a portion of a second network plane disposed within the enclosure and comprising a second plurality of interconnected switches, the second network plane being independent of the first network plane and having the same topology as the first network plane; and a plurality of connectors, each connector being communicatively coupled to a respective port of each of the first plurality of interconnected switches and the second plurality of interconnected switches.

公开(公告)号：US09830283B2

公开(公告)日：2017-11-28

申请号：US14786822

申请日：2013-05-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Gary Gostin ,  Martin Goldstein ,  Russ W. Herrell ,  Craig Warner

IPC: G06F13/14 ,  G06F13/00 ,  G06F13/20 ,  G06F13/12 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/124 ,  G06F13/4282

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

公开(公告)号：US20170255531A1

公开(公告)日：2017-09-07

申请号：US15600408

申请日：2017-05-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gostin ,  Erin A. Handgen

IPC: G06F11/16 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1666 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0683 ,  G06F11/1064 ,  G06F11/1068 ,  G11C29/74 ,  G11C29/808 ,  G11C2029/0411

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

公开(公告)号：US11481328B2

公开(公告)日：2022-10-25

申请号：US16925870

申请日：2020-07-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Alexandros Daglis ,  Paolo Faraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/0831 ,  G06F12/0811

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US11016683B2

公开(公告)日：2021-05-25

申请号：US16707946

申请日：2019-12-09

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06 ,  G06F11/10 ,  G06F9/52

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.