公开(公告)号：US12061552B2

公开(公告)日：2024-08-13

申请号：US18315806

申请日：2023-05-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/14

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US10540286B2

公开(公告)日：2020-01-21

申请号：US15967596

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S Milojicic ,  Keith Packard ,  Michael S. Woodacre ,  Andrew R Wheeler

IPC: G06F12/08 ,  G06F12/0837

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

公开(公告)号：US20230281127A1

公开(公告)日：2023-09-07

申请号：US18315806

申请日：2023-05-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/0817 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US20200349076A1

公开(公告)日：2020-11-05

申请号：US16399230

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Michael S. Woodacre ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/0817

Abstract: In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

公开(公告)号：US20190334771A1

公开(公告)日：2019-10-31

申请号：US15967583

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S Milojicic ,  Sharad Singhal ,  Andrew R. Wheeler ,  Michael S. Woodacre

IPC: H04L12/24 ,  G06F11/34 ,  G06F11/30 ,  H04L12/26 ,  H04L12/911

Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.

公开(公告)号：US20190332538A1

公开(公告)日：2019-10-31

申请号：US15967596

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Keith Packard ,  Michael S. Woodacre ,  Andrew R. Wheeler

IPC: G06F12/0837

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

公开(公告)号：US20240069742A1

公开(公告)日：2024-02-29

申请号：US17898189

申请日：2022-08-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Thomas Edward McGee ,  Brian J. Johnson ,  Frank R. Dropps ,  Derek S. Schumacher ,  Stuart C. Haden ,  Michael S. Woodacre

IPC: G06F3/06 ,  G06F12/0817

CPC classification number: G06F3/0617 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0828 ,  G06F2212/271 ,  G06F2212/621

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

公开(公告)号：US11714755B2

公开(公告)日：2023-08-01

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

CPC classification number: G06F12/0815 ,  G06F13/4027 ,  G06F2212/1032

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US11556471B2

公开(公告)日：2023-01-17

申请号：US16399230

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Michael S. Woodacre ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/0817

Abstract: In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

公开(公告)号：US11128531B2

公开(公告)日：2021-09-21

申请号：US15967583

申请日：2018-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S Milojicic ,  Sharad Singhal ,  Andrew R. Wheeler ,  Michael S. Woodacre

IPC: H04L12/24 ,  G06F11/34 ,  H04L12/911 ,  H04L12/26 ,  G06F11/30

Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.