Panoramic vision system with parallax mitigation

    公开(公告)号:US10582181B2

    公开(公告)日:2020-03-03

    申请号:US15936533

    申请日:2018-03-27

    Abstract: A panoramic image system with parallax mitigation includes image sensors, a head tracker, a display, and a processor. Each image sensor is fixedly mounted a predetermined linear distance from a first reference axis and is disposed adjacent to at least one other image sensor and to point in a direction that is offset from its adjacent image sensor by a predetermined angle. The head tracker is configured to sense at least the angular position and movement direction of a viewer's head about a second reference axis and to supply an azimuth position signal representative thereof. The display is configured to selectively display images sensed by each of the image sensors. The processor is in operable communication with the image sensors, head tracker, and display. The processor is configured, based at least on the azimuth position signal, to command the display to display images sensed by only one image sensor.

    PANAORAMIC VISION SYSTEM WITH PARALLAX MITIGATION

    公开(公告)号:US20190306484A1

    公开(公告)日:2019-10-03

    申请号:US15936533

    申请日:2018-03-27

    Abstract: A panoramic image system with parallax mitigation includes image sensors, a head tracker, a display, and a processor. Each image sensor is fixedly mounted a predetermined linear distance from a first reference axis and is disposed adjacent to at least one other image sensor and to point in a direction that is offset from its adjacent image sensor by a predetermined angle. The head tracker is configured to sense at least the angular position and movement direction of a viewer's head about a second reference axis and to supply an azimuth position signal representative thereof. The display is configured to selectively display images sensed by each of the image sensors. The processor is in operable communication with the image sensors, head tracker, and display. The processor is configured, based at least on the azimuth position signal, to command the display to display images sensed by only one image sensor.

    LOW LATENCY AUGMENTED REALITY DISPLAY
    6.
    发明申请
    LOW LATENCY AUGMENTED REALITY DISPLAY 有权
    低延迟现实显示

    公开(公告)号:US20160110919A1

    公开(公告)日:2016-04-21

    申请号:US14519457

    申请日:2014-10-21

    Abstract: An augmented reality system is provided and a method for controlling an augmented reality system are provided. The augmented reality system, for example, may include, but is not limited to a display, a memory, and at least one processor communicatively coupled to the display and memory, the at least one processor configured to generate image data having a first resolution at a first rate, store the generated image data in the memory, and transfer a portion of the generated image data having a second resolution to the display from the memory at a second rate, wherein the second rate is faster than the first rate and the second resolution is smaller than the first resolution. This dual rate system then enables a head-tracked augmented reality system to be updated at the high rate, reducing latency based artifacts.

    Abstract translation: 提供了增强现实系统,并提供了一种用于控制增强现实系统的方法。 增强现实系统例如可以包括但不限于显示器,存储器和通信地耦合到显示器和存储器的至少一个处理器,所述至少一个处理器被配置为生成具有第一分辨率的图像数据 第一速率,将生成的图像数据存储在存储器中,并且以第二速率从存储器将具有第二分辨率的所生成的图像数据的一部分传送到显示器,其中第二速率比第一速率快,而第二速率 分辨率小于第一分辨率。 这种双速率系统可以使头部追踪的增强现实系统以高速率更新,从而减少基于延迟的工件。

    SYSTEM AND METHOD OF CACHE PARTITIONING FOR PROCESSORS WITH LIMITED CACHED MEMORY POOLS
    7.
    发明申请
    SYSTEM AND METHOD OF CACHE PARTITIONING FOR PROCESSORS WITH LIMITED CACHED MEMORY POOLS 审中-公开
    具有缓存存储池的处理器缓存分区的系统和方法

    公开(公告)号:US20150205724A1

    公开(公告)日:2015-07-23

    申请号:US14159180

    申请日:2014-01-20

    Abstract: A method comprises dividing a main memory into a plurality of pools, the plurality of pools including a first pool and one or more second pools, wherein the first pool is only associated with a set of one or more lines in a first cache such that data in the first pool is only cached in the first cache and wherein the one or more second pools are each associated with one or more lines in a second cache and data in the second cache is cacheable by the first cache. The method further comprises assigning each of a plurality of threads to one of the plurality of pools and determining if a memory region being accessed belongs to the first pool. If the memory region being accessed belongs to the first pool, bypassing the second cache to temporarily store data from the memory region in the first cache.

    Abstract translation: 一种方法包括将主存储器划分成多个池,所述多个池包括第一池和一个或多个第二池,其中所述第一池仅与第一高速缓存中的一行或多行相关联,使得数据 在第一池中仅缓存在第一缓存中,并且其中一个或多个第二池分别与第二高速缓存中的一行或多行相关联,并且第二高速缓存中的数据可由第一高速缓存缓存。 所述方法还包括将多个线程中的每一个分配给所述多个池中的一个池,以及确定被访问的存储器区域是否属于所述第一池。 如果所访问的存储器区属于第一池,则绕过第二高速缓存以临时存储来自第一高速缓存中的存储器区域的数据。

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