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公开(公告)号：US20080176344A1
公开(公告)日：2008-07-24
申请号：US11625575
申请日：2007-01-22
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译： 公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于 物理特性，并根据蚀刻控制参数刻蚀该层。
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公开(公告)号：US20100120177A1
公开(公告)日：2010-05-13
申请号：US12691218
申请日：2010-01-21
IPC分类号： H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/306
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译： 公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于 物理特性，并根据蚀刻控制参数刻蚀该层。
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公开(公告)号：US20070239305A1
公开(公告)日：2007-10-11
申请号：US11390696
申请日：2006-03-28
IPC分类号： G06F19/00
摘要： Process control systems and methods for semiconductor device manufacturing are disclosed. A plurality of feedback and feed-forward loops are used to accurately control the critical dimension (CD) of features formed on material layers of semiconductor devices. Semiconductor devices with features having substantially the same dimension for each die across the surface of a wafer may be fabricated using the novel process control systems and methods described herein.
摘要翻译： 公开了用于半导体器件制造的工艺控制系统和方法。 使用多个反馈和前馈环来精确地控制在半导体器件的材料层上形成的特征的临界尺寸（CD）。 可以使用本文所述的新颖的工艺控制系统和方法来制造具有对于晶片表面上的每个管芯具有基本相同尺寸的特征的半导体器件。
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公开(公告)号：US20110250530A1
公开(公告)日：2011-10-13
申请号：US13164139
申请日：2011-06-20
CPC分类号： H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.
摘要翻译： 公开了半导体器件及其制造方法。 多个特征形成在工件上，多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸，并且第二区域中的特征具有第二横向尺寸，其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽，并且第二区域中的特征的第二横向尺寸减小。
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公开(公告)号：US08349528B2
公开(公告)日：2013-01-08
申请号：US13164139
申请日：2011-06-20
IPC分类号： G03F1/00
CPC分类号： H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.
摘要翻译： 公开了半导体器件及其制造方法。 多个特征形成在工件上，多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸，并且第二区域中的特征具有第二横向尺寸，其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽，并且第二区域中的特征的第二横向尺寸减小。
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公开(公告)号：US08007985B2
公开(公告)日：2011-08-30
申请号：US11343161
申请日：2006-01-30
IPC分类号： G03F7/20
CPC分类号： H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.
摘要翻译： 公开了半导体器件及其制造方法。 多个特征形成在工件上，多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸，并且第二区域中的特征具有第二横向尺寸，其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽，并且第二区域中的特征的第二横向尺寸减小。
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公开(公告)号：US20070178388A1
公开(公告)日：2007-08-02
申请号：US11343161
申请日：2006-01-30
CPC分类号： H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.
摘要翻译： 公开了半导体器件及其制造方法。 多个特征形成在工件上，多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸，并且第二区域中的特征具有第二横向尺寸，其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽，并且第二区域中的特征的第二横向尺寸减小。
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公开(公告)号：US07674350B2
公开(公告)日：2010-03-09
申请号：US11625575
申请日：2007-01-22
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译： 公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于 物理特性，并根据蚀刻控制参数刻蚀该层。
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公开(公告)号：US20080044741A1
公开(公告)日：2008-02-21
申请号：US11504388
申请日：2006-08-15
CPC分类号： G03F7/70425 , G03F7/70483
摘要： Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.
摘要翻译： 公开了用于光刻工艺的计量系统和方法。 在一个实施例中，制造半导体器件的方法包括提供具有形成在其上的多个圆角圆形测试图案的掩模。 提供第一半导体器件，并且使用掩模和光刻工艺，利用多个拐角圆形测试特征对第一半导体器件的感光材料层进行构图。 通过分析相对于形成在半导体器件的感光材料层上的多个角圆切削测试特征中的其它角点的多个角圆测试特征来测量光刻工艺的角圆角。 光刻处理或掩模响应于测量的角圆度的量而改变，并且提供第二半导体器件。 使用改变的光刻工艺或改变的掩模影响第二半导体器件。
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10.发明申请Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers 有权具有掺杂和未掺杂多晶硅层的半导体器件的制造方法公开(公告)号：US20110031563A1
公开(公告)日：2011-02-10
申请号：US12910239
申请日：2010-10-22
IPC分类号： H01L29/49
CPC分类号： H01L29/4916 , H01L21/28035 , H01L29/78
摘要： Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.
摘要翻译： 描述用于制造半导体器件的方法的各种说明性实施例。 这些方法可以包括例如在衬底上形成第一多晶硅层，其中第一多晶硅层包括掺杂部分，并且在第一多晶硅层的表面上形成第二多晶硅层。 而且，描述了半导体器件的各种说明性实施例，其可以通过本文所述的各种方法来制造。
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