公开(公告)号：US20120212698A1

公开(公告)日：2012-08-23

申请号：US13150715

申请日：2011-06-01

Applicant: Ho-Jun LEE ,  Sang Wook LEE ,  Sung-Jun KIM

Inventor： Ho-Jun LEE ,  Sang Wook LEE ,  Sung-Jun KIM

IPC: G02F1/1333

CPC classification number: G02F1/1341 ,  G02F1/1343 ,  G02F2202/16

Abstract: A liquid crystal display includes a first substrate and a second substrate which face each other and each include a display area and a peripheral area, a liquid crystal layer in the display areas and between the first substrate and the second substrate, and a conductive sealant combining the first substrate and the second substrate. The first substrate includes a common electrode in the display and peripheral areas of the first substrate. The second substrate includes a first and signal lines in the peripheral area of the second substrate, a first insulating layer on the first signal line and the second signal line, and a conductor on the first insulating layer in the peripheral area and connected to the first signal line through a contact hole. The common electrode includes a cutout corresponding to the conductor, and the cutout is at a corner of the display areas.

Abstract translation: 液晶显示器包括第一基板和第二基板，所述第一基板和第二基板彼此面对并且各自包括显示区域和周边区域，显示区域中的液晶层以及第一基板和第二基板之间的导电密封剂组合 第一基板和第二基板。 第一基板包括显示器中的公共电极和第一基板的外围区域。 第二基板包括在第二基板的外围区域中的第一和第二信号线，第一信号线和第二信号线上的第一绝缘层，以及周边区域中的第一绝缘层上的导体，并连接到第一基板 信号线通过接触孔。 公共电极包括对应于导体的切口，并且切口位于显示区域的拐角处。

公开(公告)号：US20120003768A1

公开(公告)日：2012-01-05

申请号：US13231225

申请日：2011-09-13

Applicant: Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

Inventor： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

IPC: H01L33/16

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20110095294A1

公开(公告)日：2011-04-28

申请号：US12875228

申请日：2010-09-03

Applicant: Ho-Jun LEE ,  Yeo-Geon YOON ,  Hyoung-Wook LEE ,  Mi-Ae LEE

Inventor： Ho-Jun LEE ,  Yeo-Geon YOON ,  Hyoung-Wook LEE ,  Mi-Ae LEE

IPC: H01L33/00 ,  H01L21/84

CPC classification number: H01L27/124 ,  H01L27/1244 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: an insulation substrate; a gate line disposed on the insulation substrate and including a compensation pattern protruding from the gate line; a first data line and a second data line both intersecting the gate line; a first thin film transistor connected to the gate line and the first data line; a second thin film transistor connected to the gate line and the second data line; and a first pixel electrode and a second pixel electrode connected to the first thin film transistor and the second thin film transistor, respectively. The first pixel electrode and the second pixel electrode share the compensation pattern.

Abstract translation: 薄膜晶体管阵列面板包括：绝缘基板; 栅极线，设置在所述绝缘基板上并且包括从所述栅极线突出的补偿图案; 第一数据线和第二数据线都与所述栅极线相交; 连接到栅极线和第一数据线的第一薄膜晶体管; 连接到栅极线和第二数据线的第二薄膜晶体管; 以及分别连接到第一薄膜晶体管和第二薄膜晶体管的第一像素电极和第二像素电极。 第一像素电极和第二像素电极共享补偿图案。

公开(公告)号：US20150357418A1

公开(公告)日：2015-12-10

申请号：US14760989

申请日：2014-01-03

Applicant: Kye-Jin LEE ,  Ho-Jun LEE ,  Young-Jae CHOI ,  Jung-Hyun EUM ,  Chung-Hyun LEE ,  LG SILTRON INC.

Inventor： Kye-Jin LEE ,  Ho-Jun LEE ,  Young-Jae CHOI ,  Jung-Hyun EUM ,  Chung-Hyun LEE

IPC: H01L29/205 ,  H01L29/20

CPC classification number: H01L29/36 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205

Abstract: Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions.

Abstract translation: 本发明提供一种半导体衬底，其包括设置在衬底上的种子层，设置在籽晶层上的缓冲层，设置在缓冲层上的多个氮化物半导体层以及多个氮化物半导体层之间的至少一个应力控制层。 缓冲层包括多个步骤区域和至少一个异质区域。 多个台阶区域包括相同的氮化物半导体材料。 异质区域包括与步骤区域不同的氮化物半导体材料。

公开(公告)号：US20100330784A1

公开(公告)日：2010-12-30

申请号：US12878225

申请日：2010-09-09

Applicant: Ho-Jun LEE ,  Yong-Jin KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ji-Hoon KIM

Inventor： Ho-Jun LEE ,  Yong-Jin KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ji-Hoon KIM

IPC: H01L21/20

CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02664

Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

Abstract translation: 提供了一种制备化合物半导体衬底的方法。 该方法包括在基板上涂覆多个球形球，在涂覆有球形球的基材上生长化合物半导体外延层，同时允许在球形球下方形成空隙，并且冷却其上化合物半导体外延层为 生长，使得衬底和化合物半导体外延层沿着空隙自我分离。 球形球处理可以减少错位几代。 此外，由于基板和化合物半导体外延层通过自分离分离，因此不需要激光剥离处理。

公开(公告)号：US20090309101A1

公开(公告)日：2009-12-17

申请号：US12435773

申请日：2009-05-05

Applicant: Dae-Cheol KIM ,  Woong-Kwon KIM ,  Sang-Youn HAN ,  In-Woo KIM ,  Ho-Jun LEE ,  Byeong-Jae AHN

Inventor： Dae-Cheol KIM ,  Woong-Kwon KIM ,  Sang-Youn HAN ,  In-Woo KIM ,  Ho-Jun LEE ,  Byeong-Jae AHN

IPC: H01L33/00 ,  H01L21/336

CPC classification number: G02F1/136213 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

Abstract: A thin film transistor array substrate and its manufacturing method are disclosed. A thin film transistor (TFT) includes a gate electrode formed on a substrate, and source and drain electrodes formed on the gate electrode and separated from each other. A common line made of the same material as the gate electrode is formed on the substrate. A storage capacitor includes a storage electrode connected with a storage electrode line and a pixel electrode formed on the storage electrode. The storage electrode and the pixel electrode are formed by patterning a transparent conductive film, and accordingly, light can be transmitted through the region where the storage capacitor is formed to thus increase an aperture ratio.

Abstract translation: 公开了薄膜晶体管阵列基板及其制造方法。 薄膜晶体管（TFT）包括形成在基板上的栅极电极和形成在栅电极上并彼此分离的源极和漏极。 在基板上形成由与栅电极相同的材料构成的公共线。 存储电容器包括与存储电极线连接的存储电极和形成在存储电极上的像素电极。 存储电极和像素电极通过图案化透明导电膜而形成，因此可以通过形成存储电容器的区域透射光，从而增加开口率。

公开(公告)号：US20120194494A1

公开(公告)日：2012-08-02

申请号：US13157374

申请日：2011-06-10

Applicant: Young-Min JUNG ,  Sang-Yeoul LIM ,  Kweon-Sam Hong ,  Hong-Joon MOON ,  You-Hyun JEONG ,  Sang-Ho KIM ,  Ho-Jun LEE

Inventor： Young-Min JUNG ,  Sang-Yeoul LIM ,  Kweon-Sam Hong ,  Hong-Joon MOON ,  You-Hyun JEONG ,  Sang-Ho KIM ,  Ho-Jun LEE

IPC: G09G3/36 ,  G02F1/1337 ,  G06F3/038

CPC classification number: G02F1/133723 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1341 ,  G02F2001/13415

Abstract: In a display panel and a method of manufacturing the same, the display panel includes a first display substrate, a second display substrate and a sealing member. The first display substrate includes a first alignment layer in a first display region and a first peripheral region of a first base substrate, and a first backflow-blocking pattern in the first peripheral region and having a curvature to surround a vertex portion of the first display region. The second display substrate includes a second alignment layer in a second display region which faces the first display region and a second peripheral region of a second base substrate. The sealing member includes a corner portion having substantially the same curvature as the first backflow-blocking pattern to surround an outline of the first and second peripheral regions.

Abstract translation: 在显示面板及其制造方法中，显示面板包括第一显示基板，第二显示基板和密封部件。 第一显示基板包括第一显示区域中的第一取向层和第一基板的第一周边区域和第一外围区域中的第一回流阻挡图案，并且具有包围第一显示器的顶点部分的曲率 地区。 第二显示基板包括与第一显示区域相对的第二显示区域中的第二取向层和第二基板的第二周边区域。 密封构件包括具有与第一回流阻挡图案基本相同的曲率的角部，以围绕第一和第二周边区域的轮廓。

公开(公告)号：US20110018815A1

公开(公告)日：2011-01-27

申请号：US12631511

申请日：2009-12-04

Applicant: Sang-Youn HAN ,  Woong-Kwon KIM ,  Dae-Cheol KIM ,  Ho-Jun LEE ,  Kyung-Ho PARK

Inventor： Sang-Youn HAN ,  Woong-Kwon KIM ,  Dae-Cheol KIM ,  Ho-Jun LEE ,  Kyung-Ho PARK

IPC: G06F3/041 ,  H01L31/042

CPC classification number: G06F3/041 ,  G06F3/042 ,  G06F2203/04103

Abstract: Provided are a touch screen panel and a method of manufacturing the same. The touch screen panel comprises: a substrate; a first reflection-preventing film formed on the substrate; a first gate wiring formed on the first reflection-preventing film; and a sensing wiring formed above the first gate wiring to be insulated from the first gate wiring and to cross the first gate wiring.

Abstract translation: 提供一种触摸屏面板及其制造方法。 触摸屏面板包括：基板; 形成在基板上的第一防反射膜; 形成在第一防反射膜上的第一栅极布线; 以及形成在所述第一栅极布线上方以与所述第一栅极布线绝缘并跨越所述第一栅极布线的感测布线。

公开(公告)号：US20100308333A1

公开(公告)日：2010-12-09

申请号：US12560652

申请日：2009-09-16

Applicant: Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

Inventor： Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

IPC: H01L33/00 ,  H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivation layer.

Abstract translation: 公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。 制造包括三掩模工艺的薄膜晶体管阵列基板的方法。 3掩模工艺包括：在衬底上形成栅极图案，在衬底上形成栅极绝缘膜，在衬底上形成源极/漏极图案和半导体图案，在第一，第二和第三钝化膜上依次形成第一，第二和第三钝化膜 基质。 在上述多层钝化膜上形成第一光致抗蚀剂图案，该第一光致抗蚀剂图案包括形成在漏电极的一部分上和在像素区域上的第一部分，以及第二部分，其中第二部分比第一部分厚， 使用第一光致抗蚀剂图案的第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除第二光致抗蚀剂图案和设置在第二光致抗蚀剂上的透明电极膜 模式; 以及在所述第二钝化层上形成透明电极图案。

公开(公告)号：US20090111250A1

公开(公告)日：2009-04-30

申请号：US12177917

申请日：2008-07-23

Applicant: Ho-Jun LEE ,  Yong-Jin KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ji-Hoon KIM

Inventor： Ho-Jun LEE ,  Yong-Jin KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ji-Hoon KIM

IPC: H01L21/20

CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02664

Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

Abstract translation: 提供了一种制备化合物半导体衬底的方法。 该方法包括在基板上涂覆多个球形球，在涂覆有球形球的基材上生长化合物半导体外延层，同时允许在球形球下方形成空隙，并且冷却其上化合物半导体外延层为 生长，使得衬底和化合物半导体外延层沿着空隙自我分离。 球形球处理可以减少错位几代。 此外，由于基板和化合物半导体外延层通过自分离分离，因此不需要激光剥离处理。