公开(公告)号：US12125938B2

公开(公告)日：2024-10-22

申请号：US15201576

申请日：2016-07-04

申请人： AZUR SPACE Solar Power GmbH

发明人： Armin Dadgar ,  Alois Krost

IPC分类号： H01L33/00 ,  H01L21/02 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

CPC分类号： H01L33/007 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/0093 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

摘要： A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising:



provision of a substrate having a silicon surface;
deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate;
optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer;
deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer;
deposition of a gallium-containing first nitride semiconductor layer on the masking layer,

wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

公开(公告)号：US12116695B2

公开(公告)日：2024-10-15

申请号：US18046953

申请日：2022-10-17

申请人： Government of the United States, as represented by the Secretary of the Air Force

发明人： Vladimir Tassev

IPC分类号： C30B25/04 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/42 ,  C30B29/44 ,  C30B29/48 ,  G02F1/355 ,  H01L21/02 ,  H01L31/18

CPC分类号： C30B25/04 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  C30B29/42 ,  C30B29/44 ,  C30B29/48 ,  G02F1/3556 ,  H01L21/02293 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/024 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02658 ,  H01L31/1828 ,  G02F1/3558

摘要： A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is H2, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), H2Te (hydrogen telluride), SbH3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H2S (hydrogen sulfide), NH3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.

公开(公告)号：US20240312780A1

公开(公告)日：2024-09-19

申请号：US18676114

申请日：2024-05-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yosuke KAJIWARA ,  Masahiko KURAGUCHI

IPC分类号： H01L21/02 ,  H01L29/04 ,  H01L29/20 ,  H01L29/40

CPC分类号： H01L21/02458 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/40

摘要： According to one embodiment, a semiconductor device includes a first transistor, and a first mounting member. The first transistor includes a nitride semiconductor layer and includes a first element electrode, a second element electrode, and a third element electrode. The first mounting member includes a first frame electrode, a plurality of first frame connection members electrically connecting the first element electrode and the first frame electrode, a first pad electrode, and a first pad connection member electrically connecting the first element electrode and the first pad electrode.

公开(公告)号：US20240304703A1

公开(公告)日：2024-09-12

申请号：US18579330

申请日：2022-07-14

申请人： UNIVERSITY OF SOUTHERN CALIFORNIA

发明人： Ajey Poovannummoottil JACOB ,  Rehan Rashid KAPADIA

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/737 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/0254 ,  H01L21/02543 ,  H01L29/2003 ,  H01L29/66318 ,  H01L29/737 ,  H01L29/7786

摘要： A method for fabricating low defective non-planar bipolar heterostructure transistors includes a steps of providing a substrate that is coated with a first dielectric layer when the substrate is not composed of a dielectric material. A layer of a first semiconductor material is formed by template liquid phase (TLP) crystal growth wherein a second dielectric layer is disposed over the first semiconductor material. A trench is patterned into the second dielectric layer. An intermediate heterostructure is formed by epitaxially growing second semiconductor material in the trench to form a fin structure therein. Various power transistor structures can be formed from the intermediate heterostructure.

公开(公告)号：US12087880B2

公开(公告)日：2024-09-10

申请号：US17652019

申请日：2022-02-22

申请人： Silanna UV Technologies Pte Ltd

发明人： Petar Atanackovic

IPC分类号： H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC分类号： H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

摘要： The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Nix1Mgy1Zn1-x1-y1)(Alq1Ga1-q1)2O4 wherein 0≤x1≤1, 0≤y1≤1 and 0≤q1≤1; and a second epitaxial oxide layer comprising (Nix2Mgy2Zn1-x2-y2)(Alq2Ga1-q2)2O4 wherein 0≤x2≤1, 0≤y2≤1 and 0≤q2≤1. In some cases, at least one condition selected from x1≠x2, y1≠y2, and q1≠q2 is satisfied.

公开(公告)号：US20240297246A1

公开(公告)日：2024-09-05

申请号：US18648169

申请日：2024-04-26

申请人： FUJITSU LIMITED

发明人： Shirou OZAKI ,  Junji KOTANI ,  Atsushi YAMADA

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes an AlN substrate, a semiconductor laminated structure, disposed above the substrate, and including an electron transit layer and an electron supply layer made of a nitride semiconductor, respectively, and a gate electrode, a source electrode, and a drain electrode disposed above the electron supply layer. The electron transit layer is located at a lowermost position of the semiconductor laminated structure. The gate electrode has a gate length of 0.3 μm or less, and a ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode is 4.0 or less.

公开(公告)号：US12080757B2

公开(公告)日：2024-09-03

申请号：US18371956

申请日：2023-09-22

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Hao Cui ,  Clifford Drowley

IPC分类号： H01L21/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306

CPC分类号： H01L29/0634 ,  H01L29/66522 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/7813 ,  H01L29/8083 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02496 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/28264 ,  H01L21/30617

摘要： A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

公开(公告)号：US12068410B2

公开(公告)日：2024-08-20

申请号：US17387433

申请日：2021-07-28

申请人： EPISTAR CORPORATION

发明人： Ya-Yu Yang ,  Shang-Ju Tu ,  Tsung-Cheng Chang ,  Chia-Cheng Liu

IPC分类号： H01L29/78 ,  H01L29/778 ,  B82Y99/00 ,  H01L21/02 ,  H01L29/20 ,  H01L29/207

CPC分类号： H01L29/78 ,  H01L29/7783 ,  B82Y99/00 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/207

摘要： A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0

公开(公告)号：US12062700B2

公开(公告)日：2024-08-13

申请号：US16374125

申请日：2019-04-03

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Michael Carroll

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0262

摘要： The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

公开(公告)号：US20240266403A1

公开(公告)日：2024-08-08

申请号：US18329881

申请日：2023-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Ming Chen ,  Kuei-Ming Chen

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.