公开(公告)号：US20100308333A1

公开(公告)日：2010-12-09

申请号：US12560652

申请日：2009-09-16

申请人： Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

发明人： Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivation layer.

摘要翻译： 公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。 制造包括三掩模工艺的薄膜晶体管阵列基板的方法。 3掩模工艺包括：在衬底上形成栅极图案，在衬底上形成栅极绝缘膜，在衬底上形成源极/漏极图案和半导体图案，在第一，第二和第三钝化膜上依次形成第一，第二和第三钝化膜 基质。 在上述多层钝化膜上形成第一光致抗蚀剂图案，该第一光致抗蚀剂图案包括形成在漏电极的一部分上和在像素区域上的第一部分，以及第二部分，其中第二部分比第一部分厚， 使用第一光致抗蚀剂图案的第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除第二光致抗蚀剂图案和设置在第二光致抗蚀剂上的透明电极膜 模式; 以及在所述第二钝化层上形成透明电极图案。

公开(公告)号：US20100006835A1

公开(公告)日：2010-01-14

申请号：US12486328

申请日：2009-06-17

申请人： Kap-Soo YOON ,  Sung-Hoon YANG ,  Sung-Ryul KIM ,  O-Sung SEO ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Seong-Hun KIM ,  Yong-Mo CHOI

发明人： Kap-Soo YOON ,  Sung-Hoon YANG ,  Sung-Ryul KIM ,  O-Sung SEO ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Seong-Hun KIM ,  Yong-Mo CHOI

IPC分类号： H01L29/786

CPC分类号： H01L27/12 ,  H01L27/1225 ,  H01L29/7869

摘要： A display substrate includes; a substrate, a gate electrode arranged on the substrate, a semiconductor pattern arranged on the gate electrode, a source electrode arranged on the semiconductor pattern, a drain electrode arranged on the semiconductor pattern and spaced apart from the source electrode, an insulating layer arranged on, and substantially covering, the source electrode and the drain electrode to cover the source electrode and the drain electrode, a conductive layer pattern arranged on the insulating layer and overlapped aligned with the semiconductor pattern, a pixel electrode electrically connected to the drain electrode, and a storage electrode arranged on the substrate and overlapped overlapping with the pixel electrode, the storage electrode being electrically connected to the conductive layer pattern.

摘要翻译： 显示基板包括： 衬底，布置在衬底上的栅电极，布置在栅电极上的半导体图案，布置在半导体图案上的源电极，布置在半导体图案上并与源电极间隔开的漏电极，布置在 并且基本上覆盖源电极和漏极以覆盖源电极和漏电极，布置在绝缘层上并与半导体图案重叠的导电层图案，与漏电极电连接的像素电极，以及 存储电极，设置在所述基板上，与所述像素电极重叠地重叠，所述存储电极与所述导电层图案电连接。

公开(公告)号：US20130234144A1

公开(公告)日：2013-09-12

申请号：US13565639

申请日：2012-08-02

申请人： O-Sung SEO ,  Hwa-Yeul OH ,  Hyoung-Cheol LEE ,  Tae-Kyung YIM

发明人： O-Sung SEO ,  Hwa-Yeul OH ,  Hyoung-Cheol LEE ,  Tae-Kyung YIM

IPC分类号： H01L27/15 ,  H01L33/08

CPC分类号： H01L27/124 ,  H01L27/3272 ,  H01L27/3279 ,  H01L29/78633

摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

摘要翻译： 通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。 更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。 像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。 第一连接提供部分将第一栅电极连接到栅极线。 另一方面，源电极从数据线整体延伸。

公开(公告)号：US20120037913A1

公开(公告)日：2012-02-16

申请号：US13167668

申请日：2011-06-23

申请人： O-Sung SEO ,  Seong-Hun KIM ,  Yang-Ho BAE ,  Jean-Ho SONG

发明人： O-Sung SEO ,  Seong-Hun KIM ,  Yang-Ho BAE ,  Jean-Ho SONG

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78618 ,  H01L29/458 ,  H01L29/66765

摘要： A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.

摘要翻译： 本文公开了一种薄膜晶体管（TFT）及其制造方法。 TFT可以包括设置在绝缘基板上的栅电极，设置在绝缘基板上的绝缘层和栅电极，设置在绝缘层上的与栅电极重叠的有源层图案，设置在绝缘层上的源电极和 其至少一部分与有源层图案重叠，以及与源电极分离并且其至少一部分与有源层图案重叠的漏电极。 可以在有源层图案和源电极之间以及有源层图案和漏电极之间设置第一欧姆接触层图案。 第一欧姆接触层在其表面上可以具有比在第一欧姆接触层的其它部分更高的氮含量。