公开(公告)号：US09054521B2

公开(公告)日：2015-06-09

申请号：US13925956

申请日：2013-06-25

申请人： Hong Kong Applied Science & Technology Research Institute Company Limited

发明人： Xiao Huo ,  Beiping Yan ,  Xiaowu Cai

IPC分类号： H02H9/00 ,  H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0248 ,  H01L27/0259

摘要： An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.

摘要翻译： 静电放电（ESD）保护电路具有垂直NPN晶体管，其具有由N +源极区域下的深p型注入产生的浮动p型基极。 深p型植入物可以是标准CMOS工艺中的ESD注入。 p型注入提供了低的初始瞬态触发电压，但是保持电压可能太低，造成闩锁问题。 通过将垂直NPN晶体管的发射极连接到并联电阻和二极管路径，保持电压提高约一伏。 当垂直NPN晶体管被触发时，其电流最初流过电阻器，当电流上升时，通过电阻产生增加的电压降。 一旦电阻上的电压达到0.5伏特，与电阻并联的二极管就会正向偏置，并分流比电阻更高的电流，提高保持电压。 钳位晶体管可以替代二极管。

公开(公告)号：US09021002B2

公开(公告)日：2015-04-28

申请号：US13760012

申请日：2013-02-05

申请人： Hong Kong Applied Science & Technology Research Institute Company Limited

发明人： Zhongzi Chen ,  Beiping Yan ,  Xiao Huo ,  Xiaowu Cai

IPC分类号： G06F1/02 ,  G06F1/03

CPC分类号： G06F1/0321 ,  G06F1/0328 ,  G06F1/0353 ,  G06F1/0356

摘要： A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

摘要翻译： 直接数字合成器（DDS）的正弦波发生器将数字相位输入转换为数字正弦波输出。 正弦值和斜率存储在只读存储器（ROM）中用于第一象限中的粗略高位相位。 象限文件夹和分相器反映和反转第一象限的值，以产生所有四个象限的幅度。 每个正弦值和斜率都存储在较低相位位的范围内。 一个Delta位分离高位和低位相位。 Delta有条件地反转低位相位，正弦值和最终极性。 减少的AND逻辑阵列将斜率乘以有条件反相的下相位位。 然后，重建的ADD逻辑阵列会添加有条件反转的正弦值。 添加有条件反转的极性以产生最终正弦值。 基于Delta位的条件反演精简生成逻辑。

公开(公告)号：US09640523B2

公开(公告)日：2017-05-02

申请号：US14847249

申请日：2015-09-08

申请人： Hong Kong Applied Science & Technology Research Institute Company Limited

发明人： Xiaowu Cai ,  Beiping Yan ,  Zhongzi Chen

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/749

CPC分类号： H01L27/0255 ,  H01L27/0262 ,  H01L29/7412 ,  H01L29/749

摘要： A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

公开(公告)号：US09305916B1

公开(公告)日：2016-04-05

申请号：US14585459

申请日：2014-12-30

申请人： Hong Kong Applied Science & Technology Research Institute Company limited

发明人： Xiaowu Cai ,  Beiping Yan ,  Xiao Huo

IPC分类号： H01L29/49 ,  H01L27/02 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/528 ,  H01L29/861

CPC分类号： H01L27/0285 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649

摘要： An Electro-Static-Discharge (ESD) protection circuit uses Silicon-On-Insulator (SOI) transistors with buried oxide but no parasitic substrate diode useable for ESD protection. A filter voltage is generated by a resistor and capacitor. When a VDD-to-VSS ESD positive pulse occurs, the filter voltage passes through an n-channel pass transistor and inverted to drive a gate of a big SOI transistor that shunts ESD current. A second path is used for a VSS-to-VDD ESD positive pulse. The filter voltage passes through a p-channel pass transistor to the gate when the positive ESD pulse is applied to VSS. The big SOI transistor can connect between VDD and VSS for a power clamp, and the gates of the n-channel and p-channel pass transistors connect to VDD. A small diode may be added between VDD and VSS to generate a small triggering current to activate grounded-gate transistors near I/O pads for full-chip Pad-based ESD protection.

摘要翻译： 静电放电（ESD）保护电路使用具有掩埋氧化物的绝缘体上硅（SOI）晶体管，但不使用可用于ESD保护的寄生衬底二极管。 滤波电压由电阻和电容产生。 当发生VDD至VSS ESD正脉冲时，滤波电压通过n沟道传输晶体管并反相，以驱动分流ESD电流的大型SOI晶体管的栅极。 第二条路径用于VSS至VDD ESD正脉冲。 当正ESD脉冲施加到VSS时，滤波器电压通过p沟道传输晶体管到栅极。 大型SOI晶体管可以在VDD和VSS之间连接电源钳位，并且n沟道和p沟道晶体管的栅极连接到VDD。 可以在VDD和VSS之间增加一个小二极管，以产生小的触发电流，以激活I / O焊盘附近的接地栅极晶体管，实现全芯片基于Pad的ESD保护。

公开(公告)号：US09356442B2

公开(公告)日：2016-05-31

申请号：US14325559

申请日：2014-07-08

申请人： Hong Kong Applied Science & Technology Research Institute Company Limited

发明人： Xiaowu Cai ,  Beiping Yan ,  Xiao Huo

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/04 ,  H01L27/0285 ,  H02H9/046

摘要： Electrostatic discharge (ESD) protection is provided by a charge-latching power-to-ground clamp circuit. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of a BigFET such as a large n-channel transistor. A transmission gate between the stages turns off when BigFET turns on, causing charge to be latched. The filter capacitor can then discharge while the BigFET remains on. A leaker resistor slowly discharges the gate of the large BigFET and turns the transmission gate back on when the BigFET turns off after shunting the ESD current. The length of time that the clamp shunts the ESD current is determined by the leaker resistor and gate capacitance of the BigFET, not by the filter capacitor, so a small filter capacitor may be used.

摘要翻译： 静电放电（ESD）保护由充电闩锁电源对地钳位电路提供。 滤波电容器和电阻器产生三级缓冲器的滤波电压，以驱动大型n沟道晶体管等BigFET的栅极。 当BigFET导通时，两级之间的传输门关闭，导致电荷被锁存。 然后，当BigFET保持导通时，滤波电容可以放电。 漏电电阻缓慢放电大型BigFET的栅极，并在分流ESD电流后BigFET关断时将传输门重新打开。 钳位分流ESD电流的时间长度由BigFET的漏电阻和栅极电容决定，而不是由滤波电容确定，因此可以使用小的滤波电容。