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    Cache which provides status information
    4.
    发明授权
    Cache which provides status information 失效
    缓存提供状态信息

    公开(公告)号：US5067078A

    公开(公告)日：1991-11-19

    申请号：US339464

    申请日：1989-04-17

    申请人： Yoav Talgam ,  James A. Klingshirn ,  James B. Gullette

    发明人： Yoav Talgam ,  James A. Klingshirn ,  James B. Gullette

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/0802 ,  G06F12/1054 ,  G06F2212/2515

    摘要： A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM). This ability to convert to a SRAM provides the first processing system with a very efficient scratch pad capability. Each cache/MMU integrated circuit also provides hit information external to the cache/MMU integrated circuit with respect to transactions on the P bus. This hit information is useful in determining system performance.

    摘要翻译： 第一处理系统沿着P总线耦合到多个集成电路。 这些集成电路中的每一个具有组合缓存和存储器管理单元（MMU）。 高速缓存/ MMU集成电路也通过M总线连接到主存储器。 第二处理系统也主要经由辅助总线而且经由M总线耦合到主存储器。 耦合在M总线和辅助总线之间的外部TAG用于维持第一和第二处理系统之间的一致性。 每个外部TAG对应于特定的高速缓存/ MMU集成电路，并且维护关于其对应的高速缓存/ MMU集成电路的状态的信息。 高速缓存/ MMU集成电路以非常有效的方式向其对应的外部TAG提供必要的状态信息。 每个高速缓存/ MMU集成电路也可以转换成SRAM模式，其中高速缓存执行像传统的高速静态随机存取存储器（SRAM）。 这种转换为SRAM的能力为第一个处理系统提供了非常高效的暂存能力。 每个缓存/ MMU集成电路还提供关于P总线上的事务的高速缓存/ MMU集成电路外部的命中信息。 该命中信息在确定系统性能方面非常有用。

    Diagnostic mode for a cache
    5.
    发明授权
    Diagnostic mode for a cache 失效
    缓存的诊断模式

    公开(公告)号：US4996641A

    公开(公告)日：1991-02-26

    申请号：US181856

    申请日：1988-04-15

    申请人： Yoav Talgam ,  Paul A. Reed ,  Elie Haddad ,  James A. Klingshirn

    发明人： Yoav Talgam ,  Paul A. Reed ,  Elie Haddad ,  James A. Klingshirn

    IPC分类号： G06F11/22 ,  G06F12/08 ,  G06F12/12 ,  G06F12/16 ,  G11C29/00 ,  G11C29/24 ,  G06F11/10

    CPC分类号： G11C29/88 ,  G06F12/0888 ,  G11C29/24

    摘要： A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.

    Method and apparatus for handling out of order exceptions in a pipelined data unit
    8.
    发明授权
    Method and apparatus for handling out of order exceptions in a pipelined data unit 失效
    用于处理流水线数据单元中的异常异常的方法和装置

    公开(公告)号：US4903264A

    公开(公告)日：1990-02-20

    申请号：US182551

    申请日：1988-04-18

    申请人： Yoav Talgam ,  Mitch K. Alsup ,  Marvin A. Denman

    发明人： Yoav Talgam ,  Mitch K. Alsup ,  Marvin A. Denman

    IPC分类号： G06F7/48 ,  G06F9/38 ,  G06F11/14

    CPC分类号： G06F7/48 ,  G06F11/1441 ,  G06F9/3863 ,  G06F7/49905

    摘要： A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

    摘要翻译： 一种用于数据处理器的流水线数据单元，该数据单元具有特殊的输入操作数检查逻辑，用于在任何一个或两个输入操作数失败时输出精确的异常处理机制，并输出结果格式逻辑以使不精确的异常处理 如果输出结果不能以选定的格式提供，那么机制。 还提供特殊缓冲器以允许每个指令独有的控制和状态信息与该指令一起流经管道。 与数据单元中正在执行的每个指令相关的足够信息被保留并且使处理程序容易获得，从而如果可以恢复，则可以处理每种类型的异常。

    Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit
    9.
    发明授权
    Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit 失效
    用于动态控制多级流水线数据单元的每个级的方法和装置

    公开(公告)号：US4893233A

    公开(公告)日：1990-01-09

    申请号：US182630

    申请日：1988-04-18

    申请人： Denman Marvin A. ,  Yoav Talgam

    发明人： Denman Marvin A. ,  Yoav Talgam

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3863

    摘要： A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

    摘要翻译： 一种用于数据处理器的流水线数据单元，该数据单元具有特殊的输入操作数检查逻辑，用于在任何一个或两个输入操作数失败时输出精确的异常处理机制，并输出结果格式逻辑以使不精确的异常处理 如果输出结果不能以选定的格式提供，那么机制。 还提供特殊缓冲器以允许每个指令独有的控制和状态信息与该指令一起流经管道。 与数据单元中正在执行的每个指令相关的足够信息被保留并且使处理程序容易获得，从而如果可以恢复，则可以处理每种类型的异常。