公开(公告)号：US11719584B2

公开(公告)日：2023-08-08

申请号：US17351675

申请日：2021-06-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu ,  Hong Liu

IPC: G01R31/28 ,  G01K7/42 ,  G01R31/26 ,  H01L23/34

CPC classification number: G01K7/425 ,  G01R31/2628 ,  G01R31/2856 ,  H01L23/34

Abstract: The disclosure relates to technology for determining stress on integrated circuits. These include using ring oscillators formed on the integrated circuit, where one ring oscillator has its frequency dependent on the current flowing through its stages being limited by its NMOS devices and another ring oscillator has its frequency dependent on the current flowing through its stages being limited by its PMOS devices. This allows the stress on the integrated circuit to be determined in different directions along the integrated circuit. A temperature sensor can be used to compensate for temperature dependence on the frequencies of the ring oscillators.

公开(公告)号：US12154890B2

公开(公告)日：2024-11-26

申请号：US17388455

申请日：2021-07-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu ,  Rui Niu ,  Tianqiang Huang

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

Abstract: A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

公开(公告)号：US20210202447A1

公开(公告)日：2021-07-01

申请号：US17199030

申请日：2021-03-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  G06F13/40

Abstract: A multi-chip module includes a first Integrated Circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, the first interleaved interconnections including a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

公开(公告)号：US20220189901A1

公开(公告)日：2022-06-16

申请号：US17687220

申请日：2022-03-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu ,  Rui Niu ,  Xiaodong Zhang ,  Yiwei Ren ,  Tonglong Zhang

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00

Abstract: A packaged IC includes a fanout layer, a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. The packaged IC further includes first conductive posts disposed beneath the first portion of the memory proximate a first side of the processor for providing communication links between the processor and memory, and second conductive posts coupled between the fanout layer and conductive features of the RDL coupled to power inputs of the second portion of the memory, the second conductive posts proximate a second side of the processor.

公开(公告)号：US20210358894A1

公开(公告)日：2021-11-18

申请号：US17388455

申请日：2021-07-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu ,  Rui Niu ,  Tianqiang Huang

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538

Abstract: A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

公开(公告)号：US11545467B2

公开(公告)日：2023-01-03

申请号：US17199030

申请日：2021-03-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shiqun Gu

IPC: G06F13/40 ,  H01L25/065 ,  H01L21/66 ,  H01L23/00

Abstract: A multi-chip module includes a first Integrated Circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, the first interleaved interconnections including a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.