Memory, Memory Use Method, Memory Manufacturing Method, and Electronic Device

    公开(公告)号:US20240331739A1

    公开(公告)日:2024-10-03

    申请号:US18741084

    申请日:2024-06-12

    CPC classification number: G11C5/063 G11C7/1048

    Abstract: This disclosure discloses a memory, a memory use method, a memory manufacturing method, and an electronic device. The memory includes a control layer and at least one storage layer stacked on the control layer. The storage layer includes a plurality of storage channels, and each storage channel includes an independent data interface bus. The control layer includes a plurality of controllers and a plurality of user interfaces, the controller is configured to access data stored in a storage channel connected to the controller. The plurality of controllers are connected to the data interface buses of the plurality of storage channels in one-to-one correspondence. A quantity of user interfaces is the same as a quantity of user storage channels that can be invoked by a user. The quantity of user interfaces is less than a quantity of controllers.

    Multi-Tier Processor/Memory Package

    公开(公告)号:US20210358894A1

    公开(公告)日:2021-11-18

    申请号:US17388455

    申请日:2021-07-29

    Abstract: A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

    Multi-tier IC package including processor and high bandwidth memory

    公开(公告)号:US12154890B2

    公开(公告)日:2024-11-26

    申请号:US17388455

    申请日:2021-07-29

    Abstract: A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

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