公开(公告)号：US20220157939A1

公开(公告)日：2022-05-19

申请号：US17369565

申请日：2021-07-07

Applicant: IMEC VZW

Inventor： Abhitosh Vais

IPC: H01L29/08 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.

公开(公告)号：US11355618B2

公开(公告)日：2022-06-07

申请号：US17103031

申请日：2020-11-24

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737 ,  H01L21/306 ,  H01L29/205

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

公开(公告)号：US11658210B2

公开(公告)日：2023-05-23

申请号：US17369565

申请日：2021-07-07

Applicant: IMEC VZW

Inventor： Abhitosh Vais

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/0817 ,  H01L29/66242 ,  H01L29/737

Abstract: The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.

公开(公告)号：US20250151312A1

公开(公告)日：2025-05-08

申请号：US18934774

申请日：2024-11-01

Applicant: IMEC VZW

Inventor： Sachin Yadav ,  Bernardette Kunert ,  Bjorn Vermeersch ,  Bertrand Parvais ,  Abhitosh Vais ,  Guillaume Boccardi ,  Annie Kumar

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/737

Abstract: Example embodiments relate to semiconductor processing methods and semiconductor components obtainable by applying the semiconductor processing methods. One example method includes providing a substrate formed of a first semiconductor material. The method also includes providing a mesa structure on the substrate and in direct contact with the substrate. The mesa structure is isolated on all lateral sides by dielectric material. Active layers of a semiconductor device are integrated in an upper portion of the mesa structure. Additionally, the method includes producing one or more openings through the dielectric material. Further, the method includes forming a cavity by removing a bottom portion of the mesa structure through the one or more openings or removing the dielectric material in a region directly adjacent to the bottom portion of the mesa structure. In addition, the method includes obtaining a thermally conductive volume by filling the cavity with a material of high thermal conductivity.

公开(公告)号：US20230395561A1

公开(公告)日：2023-12-07

申请号：US18328182

申请日：2023-06-02

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Bertrand Paravais ,  Guillaume Boccardi ,  Bernardette Kunert ,  Yves Mols ,  Sachin Yadav

IPC: H01L23/00 ,  H01L29/778 ,  H01L29/737 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L29/778 ,  H01L29/737 ,  H01L21/76898 ,  H01L21/78 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.

公开(公告)号：US20210167187A1

公开(公告)日：2021-06-03

申请号：US17103031

申请日：2020-11-24

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.