公开(公告)号：US11655558B2

公开(公告)日：2023-05-23

申请号：US16996146

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Yves Mols ,  Marina Baryshnikova

IPC: C30B25/04 ,  C30B25/10 ,  C30B25/18 ,  C30B29/42 ,  C30B29/60 ,  H01L21/762 ,  H01L21/768

CPC classification number: C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/42 ,  C30B29/60 ,  H01L21/76224 ,  H01L21/76877

Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

公开(公告)号：US20210358748A1

公开(公告)日：2021-11-18

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L29/66

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20180061712A1

公开(公告)日：2018-03-01

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/683

CPC classification number: H01L21/7813 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/8252 ,  H01L21/8258

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US11355618B2

公开(公告)日：2022-06-07

申请号：US17103031

申请日：2020-11-24

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737 ,  H01L21/306 ,  H01L29/205

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

公开(公告)号：US10340188B2

公开(公告)日：2019-07-02

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/762 ,  H01L21/683 ,  H01L21/02

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US20230395561A1

公开(公告)日：2023-12-07

申请号：US18328182

申请日：2023-06-02

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Bertrand Paravais ,  Guillaume Boccardi ,  Bernardette Kunert ,  Yves Mols ,  Sachin Yadav

IPC: H01L23/00 ,  H01L29/778 ,  H01L29/737 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L29/778 ,  H01L29/737 ,  H01L21/76898 ,  H01L21/78 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.

公开(公告)号：US11646200B2

公开(公告)日：2023-05-09

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02395 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02398 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20210167187A1

公开(公告)日：2021-06-03

申请号：US17103031

申请日：2020-11-24

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

公开(公告)号：US20210062360A1

公开(公告)日：2021-03-04

申请号：US16996146

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Yves Mols ,  Marina Baryshnikova

IPC: C30B25/04 ,  H01L21/762 ,  H01L21/768 ,  C30B29/60 ,  C30B29/42 ,  C30B25/18 ,  C30B25/10

Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.