公开(公告)号：US20230395561A1

公开(公告)日：2023-12-07

申请号：US18328182

申请日：2023-06-02

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Bertrand Paravais ,  Guillaume Boccardi ,  Bernardette Kunert ,  Yves Mols ,  Sachin Yadav

IPC: H01L23/00 ,  H01L29/778 ,  H01L29/737 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L29/778 ,  H01L29/737 ,  H01L21/76898 ,  H01L21/78 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.

公开(公告)号：US20230010039A1

公开(公告)日：2023-01-12

申请号：US17859294

申请日：2022-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Martin Heilmann ,  Ming Zhao ,  Nadine Collaert ,  Bertrand Parvais ,  Sachin Yadav

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/02 ,  C30B29/06 ,  C30B25/18 ,  C30B29/40 ,  C23C16/30 ,  C23C16/02

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

公开(公告)号：US20230395376A1

公开(公告)日：2023-12-07

申请号：US18324752

申请日：2023-05-26

Applicant: IMEC vzw

Inventor： Bertrand Parvais ,  Sachin Yadav ,  Ming Zhao ,  Pieter Cardinael

IPC: H01L21/02 ,  H01L21/322 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/02181 ,  H01L21/3223 ,  H01L29/2003 ,  H01L21/02381 ,  H01L21/02164 ,  H01L21/0245 ,  H01L21/02532

Abstract: In one aspect, a substrate includes a base substrate, a dielectric layer directly on the base substrate, a trap-rich layer directly on the dielectric layer, and a crystalline semiconductor layer directly on the trap-rich layer. The dielectric layer may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate can be suitable to epitaxially grow on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor. One application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable to process in and/or on the layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, can enable the neutralization of a parasitic surface conductive (PSC) layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer. The disclosed technology is equally related to methods of producing the substrate of the disclosed technology.