公开(公告)号：US20160118542A1

公开(公告)日：2016-04-28

申请号：US14989114

申请日：2016-01-06

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L33/40 ,  H01L29/207 ,  H01L33/32 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/20 ,  H01L21/324

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

公开(公告)号：US20150162212A1

公开(公告)日：2015-06-11

申请号：US14551398

申请日：2014-11-24

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L21/3205 ,  H01L21/3213

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Abstract translation: 公开了一种在半导体器件中制造互补金属氧化物半导体（CMOS）兼容接触层的方法。 在一个实施例中，镍（Ni）层沉积在GaN基结构的p型氮化镓（GaN）层上。 此外，在350℃至500℃的温度范围内对GaN基结构进行热处理。此外，使用蚀刻剂除去Ni层。 此外，在去除Ni层之后，在p型GaN层上沉积CMOS兼容的接触层。

公开(公告)号：US09698309B2

公开(公告)日：2017-07-04

申请号：US14989114

申请日：2016-01-06

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L33/40 ,  H01L21/8252 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/20 ,  H01L29/45 ,  H01L33/32 ,  H01L29/207

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

公开(公告)号：US11114537B2

公开(公告)日：2021-09-07

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L21/3213

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

公开(公告)号：US20200235218A1

公开(公告)日：2020-07-23

申请号：US16748192

申请日：2020-01-21

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Niels Posthuma ,  Brice De Jaeger

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/66

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.