公开(公告)号：US09698309B2

公开(公告)日：2017-07-04

申请号：US14989114

申请日：2016-01-06

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L33/40 ,  H01L21/8252 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/20 ,  H01L29/45 ,  H01L33/32 ,  H01L29/207

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

公开(公告)号：US20150162212A1

公开(公告)日：2015-06-11

申请号：US14551398

申请日：2014-11-24

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L21/3205 ,  H01L21/3213

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Abstract translation: 公开了一种在半导体器件中制造互补金属氧化物半导体（CMOS）兼容接触层的方法。 在一个实施例中，镍（Ni）层沉积在GaN基结构的p型氮化镓（GaN）层上。 此外，在350℃至500℃的温度范围内对GaN基结构进行热处理。此外，使用蚀刻剂除去Ni层。 此外，在去除Ni层之后，在p型GaN层上沉积CMOS兼容的接触层。

公开(公告)号：US11282702B2

公开(公告)日：2022-03-22

申请号：US17068785

申请日：2020-10-12

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN

Inventor： Philippe Soussan ,  Vasyl Motsnyi ,  Luc Haspeslagh ,  Stefano Guerrieri ,  Olga Syshchyk ,  Bernardette Kunert ,  Robert Langer

IPC: H01L27/00 ,  H01L21/02 ,  H01L29/66

Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.

公开(公告)号：US20160118542A1

公开(公告)日：2016-04-28

申请号：US14989114

申请日：2016-01-06

Applicant: IMEC VZW

Inventor： Celso Cavaco ,  Brice De Jaeger ,  Marleen Van Hove ,  Vasyl Motsnyi

IPC: H01L33/40 ,  H01L29/207 ,  H01L33/32 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/20 ,  H01L21/324

CPC classification number: H01L33/40 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/3245 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/452 ,  H01L33/32 ,  H01L33/325 ,  H01L2933/0016

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

公开(公告)号：US20150115277A1

公开(公告)日：2015-04-30

申请号：US14520763

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Vasyl Motsnyi ,  Barundeb Dutta ,  Maarten Rosmeulen

IPC: H01L29/20 ,  H01L33/12 ,  H01L21/306 ,  H01L29/201 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L29/2003 ,  B24B37/042 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30625 ,  H01L29/201 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32

Abstract: The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate.

Abstract translation: 实施方式公开了具有III-V族材料的硅衬底和在硅衬底上制造III-V族材料的方法。 该方法包括提供硅衬底。 形成在硅衬底顶上的第一层随后被图案化以暴露下面的硅衬底。 在图案化的第一层上以及暴露的硅衬底上形成III-V族材料层。 对III-V族材料层进行化学机械抛光（CMP）以暴露第一层，从而形成适于在硅衬底上生长器件层的多个区域。