HARDWARE IMPLEMENTATION OF A TEMPORAL MEMORY SYSTEM

    公开(公告)号:US20180046899A1

    公开(公告)日:2018-02-15

    申请号:US15650749

    申请日:2017-07-14

    Applicant: IMEC VZW

    Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

    Machine Learning-based Tool to Characterize Individual Oxide Defects

    公开(公告)号:US20250147094A1

    公开(公告)日:2025-05-08

    申请号:US18936911

    申请日:2024-11-04

    Abstract: A method, system, and non-transitory computer-readable medium for characterizing oxide defects in semiconductor devices are described. Based on time-resolved SILC data, a total number of active oxide defects and each defect's characteristics can be determined for a deeply-scaled FET device. The discrete changes in leakage current correspond to switching of a single defect. A Bayesian-inspired algorithm is utilized to extract distinct current levels and experimental data is quantized into these extracted current levels by filtering noise. The evolution of current levels corresponds to a Markov chain. The defect currents are extracted by clustering transition probabilities and absolute differences in current levels using an affinity propagation algorithm. A maximum likelihood estimator is developed to extract a base leakage current. Lastly, defect currents are used to reconstruct the experimental data and its deconvolution into activity of individual defects provides the respective time

    Switching device with active portion configured to switch between insulating state and conducting state

    公开(公告)号:US10680597B2

    公开(公告)日:2020-06-09

    申请号:US16414609

    申请日:2019-05-16

    Applicant: IMEC vzw

    Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

    SWITCHING DEVICE WITH ACTIVE PORTION CONFIGURED TO SWITCH BETWEEN INSULATING STATE AND CONDUCTING STATE

    公开(公告)号:US20190356308A1

    公开(公告)日:2019-11-21

    申请号:US16414609

    申请日:2019-05-16

    Applicant: IMEC vzw

    Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

    Hardware implementation of a temporal memory system

    公开(公告)号:US10452972B2

    公开(公告)日:2019-10-22

    申请号:US15650749

    申请日:2017-07-14

    Applicant: IMEC VZW

    Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

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