公开(公告)号：US20140377936A1

公开(公告)日：2014-12-25

申请号：US14313928

申请日：2014-06-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Liesbeth Witters ,  Roger Loo

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.

Abstract translation: 本发明涉及形成应变半导体结构的方法。 该方法包括提供应变松弛缓冲层，在应变松弛缓冲层上形成牺牲层，通过牺牲层形成浅沟槽隔离结构，去除牺牲层上的氧化物层的至少一部分，蚀刻通过牺牲层 使得应变松弛缓冲层的一部分被暴露，在应变松弛缓冲层的暴露部分上形成应变半导体结构。

公开(公告)号：US09640411B2

公开(公告)日：2017-05-02

申请号：US14934111

申请日：2015-11-05

Applicant: IMEC VZW

Inventor： Jianwu Sun ,  Roger Loo

IPC: H01L29/06 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/161 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/32055 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.

公开(公告)号：US09502415B2

公开(公告)日：2016-11-22

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。

公开(公告)号：US09478544B2

公开(公告)日：2016-10-25

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括提供具有由介电材料结构限定的侧壁并邻接在硅衬底表面上的侧壁的沟槽，以及在表面上的沟槽中生长晶种层， 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US20160126109A1

公开(公告)日：2016-05-05

申请号：US14934111

申请日：2015-11-05

Applicant: IMEC VZW

Inventor： Jianwu Sun ,  Roger Loo

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/161 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/32055 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.

Abstract translation: 一种用于制造在硅基衬底上的锗通道材料的晶体管器件的方法，所述方法包括提供浅沟槽隔离（STI）衬底，所述浅沟槽隔离（STI）衬底包括嵌入在STI电介质结构中的硅突起，并且部分地使所述硅突起凹陷， 在相邻的STI结构之间的沟槽，并且在凹入突起的上表面处提供V形槽。 该方法还包括在沟槽中生长Si1-xGex SRB层，并在Si1-xGex SRB层上生长基于锗的沟道层。 在该实施例中，Si1-xGex SRB层包含在20％至99％的范围内的锗含量x，并且SRB层具有小于400nm的厚度。 本公开还涉及相关联的晶体管器件。

公开(公告)号：US09299563B2

公开(公告)日：2016-03-29

申请号：US14313928

申请日：2014-06-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Liesbeth Witters ,  Roger Loo

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/10 ,  H01L21/3065

CPC classification number: H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.

Abstract translation: 本发明涉及形成应变半导体结构的方法。 该方法包括提供应变松弛缓冲层，在应变松弛缓冲层上形成牺牲层，通过牺牲层形成浅沟槽隔离结构，去除牺牲层上的氧化物层的至少一部分，蚀刻通过牺牲层 使得应变松弛缓冲层的一部分被暴露，在应变松弛缓冲层的暴露部分上形成应变半导体结构。

公开(公告)号：US20160027780A1

公开(公告)日：2016-01-28

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括：提供具有由介电材料结构限定的侧壁并邻接在硅衬底的表面上并具有在表面上的沟槽中的种子层的沟槽，其中 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US20160027779A1

公开(公告)日：2016-01-28

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。

公开(公告)号：US20210336002A1

公开(公告)日：2021-10-28

申请号：US17240694

申请日：2021-04-26

Applicant: IMEC VZW

Inventor： Roger Loo ,  Geert Eneman ,  Clement Porret

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.