公开(公告)号：US20190318082A1

公开(公告)日：2019-10-17

申请号：US16452916

申请日：2019-06-26

Applicant: INTEL CORPORATION

Inventor： ABHISHEK BASAK ,  RAVI SAHITA ,  VEDVYAS SHANBHOGUE

IPC: G06F21/52 ,  G06F12/06

Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.

公开(公告)号：US20170177505A1

公开(公告)日：2017-06-22

申请号：US14975588

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： ABHISHEK BASAK ,  SIDDHARTHA CHHABRA ,  JUNGJU OH ,  DAVID M. DURHAM

IPC: G06F12/14 ,  H04L9/06 ,  G06F3/06 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F21/79 ,  G06F3/0623 ,  G06F3/0661 ,  G06F3/0673 ,  G06F7/724 ,  G06F12/0886 ,  G06F12/0891 ,  G06F12/124 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/60 ,  G06F2212/70 ,  H03M13/15 ,  H04L9/0637 ,  H04L9/3242 ,  H04N19/463 ,  H04N19/93

Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.

公开(公告)号：US20230098288A1

公开(公告)日：2023-03-30

申请号：US17485421

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Ravi SAHITA ,  Utkarsh Y i wil ,  ABHISHEK BASAK ,  LEE ALBION ,  FILIP SCHMOLE ,  RUPIN VAKHARWALA ,  VINIT M ABRAHAM ,  RAGHUNANDAN MAKARAM

IPC: G06F21/54 ,  G06F9/455 ,  G06F21/56 ,  G06F13/40

Abstract: Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine whether to allow a read or write transaction directed to a protected register to proceed over the interconnect fabric, the security hardware logic to evaluate one or more security attributes associated with an initiator of the transaction to make the determination.

公开(公告)号：US20220091851A1

公开(公告)日：2022-03-24

申请号：US17029335

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  ALAA ALAMELDEEN ,  ABHISHEK BASAK ,  SCOTT CONSTABLE ,  FRANCIS MCKEEN ,  JOSEPH NUZMAN ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  XIANG ZOU

IPC: G06F9/38 ,  G06F9/48 ,  G06F21/54 ,  G06F9/30

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (μop) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing μop. Other embodiments are described and claimed.

公开(公告)号：US20180341767A1

公开(公告)日：2018-11-29

申请号：US15605573

申请日：2017-05-25

Applicant: INTEL CORPORATION

Inventor： ABHISHEK BASAK ,  RAVI L. SAHITA ,  VEDVYAS SHANBHOGUE

IPC: G06F21/52 ,  G06F12/06

CPC classification number: G06F21/52 ,  G06F12/06 ,  G06F2212/1008 ,  G06F2212/1052 ,  G06F2212/154 ,  G06F2221/033

Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.