公开(公告)号：US20180067533A1

公开(公告)日：2018-03-08

申请号：US15689646

申请日：2017-08-29

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US20210325952A1

公开(公告)日：2021-10-21

申请号：US17357479

申请日：2021-06-24

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US11061463B2

公开(公告)日：2021-07-13

申请号：US15689646

申请日：2017-08-29

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US20190056761A1

公开(公告)日：2019-02-21

申请号：US16036419

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

IPC: G06F1/12 ,  G06F13/42

CPC classification number: G06F1/12 ,  G06F13/4291

Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

公开(公告)号：US11650652B2

公开(公告)日：2023-05-16

申请号：US17357479

申请日：2021-06-24

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

CPC classification number: G06F1/325 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/00

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US10599178B2

公开(公告)日：2020-03-24

申请号：US16036419

申请日：2018-07-16

Applicant: Intel Corporation

Inventor： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

IPC: G06F1/12 ,  G06F13/42

Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

公开(公告)号：US09753526B2

公开(公告)日：2017-09-05

申请号：US14581854

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.