公开(公告)号：US20150089201A1

公开(公告)日：2015-03-26

申请号：US14562310

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract translation: 一个方面的方法可以包括接收旋转指令。 旋转指令可以指示源操作数和旋转量。 结果可以存储在由旋转指令指示的目标操作数中。 结果可能使源操作数旋转了旋转量。 旋转指令的执行可以在不读取进位标志的情况下完成。

公开(公告)号：US11106461B2

公开(公告)日：2021-08-31

申请号：US15939693

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US11900108B2

公开(公告)日：2024-02-13

申请号：US17461949

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US20150089200A1

公开(公告)日：2015-03-26

申请号：US14562223

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US20150089199A1

公开(公告)日：2015-03-26

申请号：US14562145

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US08738893B2

公开(公告)日：2014-05-27

申请号：US13802540

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Vindoh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/3001 ,  G06F9/30094

Abstract: A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Abstract translation: 一方面的方法可以包括接收添加指令。 加法指令可以指示第一源操作数，第二源操作数和第三源操作数。 作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。 该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。 还公开了其它方法，以及机器可读介质上的装置，系统和指令。

公开(公告)号：US20220107806A1

公开(公告)日：2022-04-07

申请号：US17461949

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US10649774B2

公开(公告)日：2020-05-12

申请号：US15855575

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Gilbert M. Wolrich ,  Martin G. Dixon ,  Mark C. Davis ,  Sean P. Mirkes ,  Alexandre J. Farcy ,  Bret L. Toll ,  Maxim Loktyukhin

IPC: G06F9/30

Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

公开(公告)号：US10409612B2

公开(公告)日：2019-09-10

申请号：US14998249

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F12/084 ,  G06F12/0895 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/1045 ,  G06F12/0806

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US10409611B2

公开(公告)日：2019-09-10

申请号：US14998248

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F12/084 ,  G06F12/0895 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/1045 ,  G06F12/0806

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.